Connect with us

most appropriate high speed interface

Discussion in 'Electronic Basics' started by Jan van Timpeln, Jan 11, 2006.

Scroll to continue with content
  1. Hello community,

    I am a student of electrical engineering and in the course of a laboratory I
    am currently designing a serdes chip and looking for an adequate interface
    for the I/Os.
    Power dissipation an chip space are the most relevant aspects. What I do is
    a 10Gbit/s to 1 Gbit/s deserializing. On the input I am using LVDS signals,
    so what would be an appropriate signalling on the output for 1Gbit/s
    signals? Is it possible to transmit 1 Gbit/s single ended or do I need to
    use differential signalling? Unfortunately that means double the pad number
    and thus double chip space, but chip space is expensive.
    Because the supply budget is limited I want a minimum on power dissipated at
    the output buffers. What transmission standard would be advisable in that

    Thank you very much in advance
  2. Joseph2k

    Joseph2k Guest

    If the design were for the most common 9.6 GB/s system then 8 to 1 is the
    correct ratio. Or 4 to 1 or 16 to 1. At 16 to 1 single ended becomes
    bad choice of follow up groups, this not a cad issue currently.
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day