Lord_grezington
- May 3, 2013
- 124
- Joined
- May 3, 2013
- Messages
- 124
I have one final question (hopefully)
Gate charge = 10nC
Voltage @ gate charge is 0 up to 4.5V
So C = Q/V = 10/4.5 = 2.22nF gate capacitance
So, If i were to run on 10V, Q = 2.22nF x 10V = 22.2nC (gate charge increases)
Ok, now we limit the current to say 0.5A (Mosfet driver limit)
t = Q/I = 22.2/0.5 = 44.4ns transition time @ 10V
t = 10/0.5 = 20ns transition time @ 5V
So increasing the gate voltage increases switching losses???
There needs to be some sort of other bias here as well because I also noticed that the data sheet states the switching time using Vgs = 10V and state the Qg @ 4.5V. This means that as Infineon want to make their stuff look good they would give the faster switching times @ 10V, so this contradicts the calculations.
Please tell me I have done something wrong here?
Thanks
Gate charge = 10nC
Voltage @ gate charge is 0 up to 4.5V
So C = Q/V = 10/4.5 = 2.22nF gate capacitance
So, If i were to run on 10V, Q = 2.22nF x 10V = 22.2nC (gate charge increases)
Ok, now we limit the current to say 0.5A (Mosfet driver limit)
t = Q/I = 22.2/0.5 = 44.4ns transition time @ 10V
t = 10/0.5 = 20ns transition time @ 5V
So increasing the gate voltage increases switching losses???
There needs to be some sort of other bias here as well because I also noticed that the data sheet states the switching time using Vgs = 10V and state the Qg @ 4.5V. This means that as Infineon want to make their stuff look good they would give the faster switching times @ 10V, so this contradicts the calculations.
Please tell me I have done something wrong here?
Thanks