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mosfet help (ltspice question)

Discussion in 'Electronic Design' started by Rick, Jan 8, 2004.

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  1. Rick

    Rick Guest

    I am learning ltspice (or at least trying to) and I have a question about
    the built in mosfets. Actually, this is a question about mosfets in general
    I guess:

    Ok, so I placed a Si4892DY n-fet from the included parts library on a new
    schematic, connected the gate to the drain, the source to ground, and the
    drain to +10V DC through a 10Meg resistor. After simulating with the .OP
    command I measured a drain voltage of 2.00015V. Assuming this to be the
    threshold voltage (Vt) I then simulated the same circuit with a 1K resistor
    in place of the 10Meg (from drain to +10V). I measured a drain voltage of
    2.01515V and a drain current of 7.98485mA.

    Ok, so plugging these into the equation Id = 0.5k(Vgs-Vt)^2 I find k =
    70.98A/V^2.

    Doesn't this seem like a huge value of k for this part?

    I got into this when I was trying to model a CD4007 Texas Instruments part
    which has a very spice unfriendly datasheet.

    What range of k should I expect for smallish mosfets?

    Thanks,

    Rick
     
  2. Rick wrote...
    Excuse me? The Si4892, capable of 12A and with Rds = 0.012 ohms, is not
    a smallish mosfet! It may not have a very large die, but it's part of the
    DMOS family of MOSFETs that have a vertical "V" structure that greatly
    increases the surface area over flat parts like the '4007. So, yes it'll
    have a very large k, exactly as a "big" part like the Si4892 should.

    While we're on the subject of power FET spice models at low currents, let
    me give you the bad news, they don't. That is, the power MOSFET spice
    models offered up may have pleasant accuracies in the high-power region,
    but they are generally woefully wrong in the subthreshold region (where
    the FET in fact acts like a transistor with exponential characteristics,
    see AoE page 123), and in the threshold-onset region. In fact the models
    are often dramatically wrong even well above the currents represented by
    the data sheet's gate-voltage threshold spec. I've often written about
    this issue on these pages, including lots of measured data to illustrate
    the sobering point. Sobering, that is, for those who like to use (and
    model) elegant power large MOSFETs in the linear class-A region.

    In the next edition of AoE we'll deal with this sad issue in more detail.

    Thanks,
    - Win

    whill_at_picovolt-dot-com
     
  3. Rick

    Rick Guest

    Oh...heh heh, I guess that explains the W=1208729u L=0.50u dimensions in the
    spice file I found on the vishay site
    (http://www.vishay.com/docs/75433/4892p.txt)

    lol, that would be a width of 1.2 meters...well I guess that explains the
    high k figure :)

    I will reread your notes in AOE, and keep in mind the mosfet models I use
    may not represent reality at all currents.

    Thanks,

    Rick
     
  4. Surely that's only the case for power FETs designed primarily for
    switching, though? There are other ones used in the PA stages of audio
    amplifiers and one assumes the manufacturers provide SPICE models for
    those which reflect the intended application in the sub-threshold
    region??
     
  5. Nope. Its unlikely that any manufacture will provide decent
    sub-threshold modelling for discreet parts. If you are doing i.c.
    design, you can often get accurate models from the fab.

    One of the golden rules of i.c. design is. "never operate a device in
    subthreshold". One does all ones main design work *explicitly* ensuring
    that the there is a minimum Vgst, say 100mv over all conditions. So, the
    usual intention is that subthreshold is not being used.

    Only if all else fails in a design approach should you usually
    contemplate subthreshold operation. Often a sign off by the boss is
    required. There is an exception, that I will leave for the interested
    reader to figure out.

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.

    That which is mostly observed, is that which replicates the most.
    http://www.anasoft.co.uk/replicators/index.html

    "quotes with no meaning, are meaningless" - Kevin Aylward.
     
  6. subject was: mosfet help (ltspice question)

    Kevin Aylward wrote...
    You make the point before and an aspect of it needs to be refuted.

    Your comments may be valid for IC design, where one may simply
    scale down the FET size until the current density reaches the
    desired level. However your advice is decidedly wrong for discrete
    linear circuit designers, who are forced to select from available
    commercial power MOSFETs.

    For example, we show measurements (AoE pg 123) of two of Supertex'
    smallest DMOS FETs, the VN-01 and VP-01. For these N and P-type
    FETs subthreshold-operation crossover occurs in the 10mA region.
    So any use of these FETs as linear components at currents below
    say 5mA will be subthreshold. Rest assured there are many such
    uses. Also, the gate voltage is about 2.5V for the VP-01 in this
    region, which the last time I checked is well above 100mV. :>)

    [Note to readers: "subthreshold" is a semiconductor FET device-
    physics term and is not directly related to the gate-threshold
    specification found on FET data sheets. For example, the VP01's
    specs are -3.5V max at 1mA, which is not so far from 10mA. But
    many large FETs have gate-threshold specs at 250uA, whereas they
    are in the subthreshold region below 100mA, 250mA or even higher.
    In a data sheet, below threshold means a switched FET is "off".]

    Subthreshold theory is useful to linear power-amplifier designers.
    Here the designer necessarily chooses large die-area FETs in order
    to obtain low thermal resistance. Yet he may want to bias them at
    modest class AB currents, say 50 to 100mA. This is squarely within
    the low current-density region for large FETs, and requires using
    subthreshold math for accurate analysis. The designer would also
    like to understand and model the FET operation in the 0 to 100mA
    region to explore the bias and crossover properties of his circuit.

    Subthreshold operation is common for high-voltage FETs, whether in
    amplifier stages, or for other purposes, such as for high-impedance
    high-voltage probes. Low-level high-voltage current sources are
    another example. In many of these cases one is forced to use much
    larger FETs than would seem necessary for the task, forcing one to
    operate squarely in the subthreshold region.

    Subthreshold FET operation is not to be feared, IMHO. It's very
    predictable, with drain current exponentially related to Vgs and
    transconductance proportional to current, just like a transistor.

    However, one does suffer two penalties for using a FET with more
    than the optimal surface area. As expected one is higher leakage
    current, but fortunately these currents are usually surprisingly
    low, so this is rarely a problem.

    The serious penalty from using a large FET at low currents is an
    excessively high capacitance. This aspect can be very painful in
    many aplications working at moderately-high frequencies or with
    high-impedance nodes. But unlike an IC designer who simply makes
    a smaller FET, the discrete circuit designer must find work-arounds
    to the issue. That is, after first scouring the world for smaller
    FETs. For one type at least, high-voltage FETs, most manufacturers
    have discontinued the attractive small parts they once offered. So
    I've learned to grab and inventory small FETs whenever one shows up.

    Thanks,
    - Win

    whill_at_picovolt-dot-com
     
  7. But you comments below don't refute what I said. You indicate that one
    might not have a choice. So,

    What part of "if all else fails" did you misunderstand? :)
    No its not. My advice is to avoid it whenever possible. This is sound
    advice, and I stand by it.
    So, What part of "if all else fails" did you misunderstand?
    I did not say it as never usefull, I said avoid it were ever possible.
    But the math is *never* used in practise for this bias setting. One
    typically uses a pot across the gates and sets it by measuring the
    current. Hint: remember my 500W per Chan mosfet amp:)

    The math can't be used for the real physical unit as you don't have the
    data for each individual device. The device to device spread is way too
    much, just as it is for a bipolar class AB.
    It is, as you don't get the manufactures data and guarantees of
    performance.
    Its not for current mirrors. There is wide variation for Vds.
    You can use the CD4007 for many low voltage jobs.

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.

    "That which is mostly observed, is that which replicates the most"
    http://www.anasoft.co.uk/replicators/index.html

    "quotes with no meaning, are meaningless" - Kevin Aylward.
     
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