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mos transistor modelling

Discussion in 'Electronic Components' started by [email protected], Jun 20, 2005.

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  1. Guest

    hi,
    I'm looking at modelling of the process variations in mos
    transistor at say 90nm and below. I'm new to this group, and
    not sure where exactly to post it.

    Basically, the foundry guys give the standard deviation
    data on vt, transconductance and Idss. With this I would like
    to figure out how the (say)inverter delays are affected.
    (Essentially try and figure out the distribution).

    In my opinion, all the three are not totally uncorrelated
    to each other. So, I presume selecting two of these should
    do a good job. Is this on the right track??

    And if someone has worked on these things can he/she share
    some basic ideas with me??

    ganesh
     
  2. I hope you mean by using spice. Any other way is daft.
    Standard i.c. design practise is to do worst case runs of strong/fast,
    nominal/normal and weak/slow. See for example,
    http://www.anasoft.co.uk/worstcase.html and
    http://www.anasoft.co.uk/WCSETUP.GIF

    You need to vary the mosfet capacitances as well.

    If you use SS, you only only have to specify two special "multiplier
    models", and runs are all automated for that device. You don't have to
    work it out yourself.

    multiplier are values that multiply nominal values, e.g.

    ..MODEL ss_wc_nch_xw nmos(tox=1.033 vth0=1.25 cj=1.05 cjsw=1.05 cgdo=1.05
    cgso=1.05)

    ..MODEL ss_wc_nch_xs nmos(tox=960m vth0=750m cj=950m cjsw=950m cgdo=950m
    cgso=950m)

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
     
  3. Guest

    hi Kevin,
    thanks for the information. But I'm actually looking for something
    slightly different.
    Its my mistake, since I didnt mention it clearly or rather not mention
    it at all.

    I'm looking at on chip variations. So, modelling the entire design at
    SS or FF is too pessimistic.
    So, within the same chip, vt etc of the transistors are going to vary.
    I can take this into account if I do a statistical modelling (both at
    SS and FF).
    So, I get the delays as a probability distribution.

    So, for a given value of vt, transconductance etc, I run spice and get
    the delay.
    Now, I vary these parameters accroding to some probability and get
    various delays with various probabilities.
    This way I can take care of on chip variations probabilistically.

    Now, the issue is getting into the exact details of the modelling.
    Every parameter vt, cgdo, cgso, gm, idss, AS, AD etc will vary. The
    idea is to take uncorrelated parameters
    as much as possible. Also if I take too many parameters, its difficult
    to model.
    So I would like to take some 2 or 3 dominant guys. I'm thinking of vt
    and transconductance.
    Are these choices ok??


    ganesh
     
  4. Try sci.engr.semiconductors
     
  5. Frank Moe

    Frank Moe Guest

    Hi,
    take about 10% of the worst case variation as the relative variation
    across the chip as long as the chip is reasonably siced.
    Frank
     
  6. It can be, but it it don't really matter if you can actually achieve a
    design that meets spec anyway. You usually only need to try and fine
    tune the calculation if the worst case design looks like the design wont
    make it.

    I personally use that fact that wc can give a pessimistic answer to give
    me more confidence that the design will work for the conditions that are
    either not checked, or the models themselves are not accurate enough.
    My personal view is that this approach (MC) is not that wonderfull. The
    reason being that, imo, one needs very large numbers of runs to account
    for all conditions. Transient runs can take a long time.
    That's why one often just does worst case. Its a compromise between
    simulation time and accurate results.

    I can tell you one thing though, in many companies, unless you do a wc
    set of runs, you wont get a sign off from your manager to get masks
    made.

    What ever you do n addition, realistically, it *must* pass WC (not MC)
    to go to fab. End of story.
    I noted in the other post what *are* the dominant ones to consider, you
    probaly missed this point being made, so I will repeat it:

    These are the wc ratios (3 sigma) provided by a well known fab house.

    ..MODEL ss_wc_nch_xw nmos(tox=1.033 vth0=1.25 cj=1.05 cjsw=1.05 cgdo=1.05
    cgso=1.05)

    ..MODEL ss_wc_nch_xs nmos(tox=960m vth0=750m cj=950m cjsw=950m cgdo=950m
    cgso=950m)

    tox effectively varies the transconductance as the transconductance
    parameter k=u.epsilon/tox

    The above are the variations typically provided by fab houses. They
    don't provide much data on the other parameters in the BSim3 models.

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
     
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