R
Roger Bourne
- Jan 1, 1970
- 0
Hello all,
Lately, I've been going over esd protection schemes. Many ESD
protection are referred to as *snap* type or *snapback*. Looking into
the snapback caracteristics of a MOS device, I found myself extremely
confused. (There a very helpful thesis link for this topic which I
obtained by an earlier post. I forgot which post).
This is the snapack I-V of NMOS (view in fixed font):
(Ids)
/
/
/
/
/
----------- <--2nd knee
\
/
/
/
------------------------ <-- 1st knee
Vsb Vbd
(Vds)
If the the ESD protection if of *snap* type (esd protection consists
only of grounded nmoses) does it mean (according to the above diagram)
that the device is protected by the fact that an ESD event is expected
to place the ESD nmos to the snapback voltage?
In other words, the current will increase causing the vds too also
increase until it reaches the part in the curve where there is
negative resistance (2nd knee), at which point the Vds will snap back
to the Vsb voltage. Hence, during an ESD event the pad voltage will be
pulled back to Vsb.
Won't that place the device in a state from which it cannot exit ?
I mean that if the ESD current discharge stops when the mos device is
beyond the 2nd knee, won't the nmos be stuck at at voltage below Vbd?
I have trouble imagining that the Vds voltage will increase as the
current lowers in order for the nmos to go back to the origin of the I-
V curve.
Also, in order to reach the 1st knee of the curve, won't the esd mos
allow voltages to pass that are above the oxide breakdown voltage
(BVox), thus causing irreparable harm to any gates connected to that
pad ?
Any help will be appreciated.
Thank you
-Roger
Lately, I've been going over esd protection schemes. Many ESD
protection are referred to as *snap* type or *snapback*. Looking into
the snapback caracteristics of a MOS device, I found myself extremely
confused. (There a very helpful thesis link for this topic which I
obtained by an earlier post. I forgot which post).
This is the snapack I-V of NMOS (view in fixed font):
(Ids)
/
/
/
/
/
----------- <--2nd knee
\
/
/
/
------------------------ <-- 1st knee
Vsb Vbd
(Vds)
If the the ESD protection if of *snap* type (esd protection consists
only of grounded nmoses) does it mean (according to the above diagram)
that the device is protected by the fact that an ESD event is expected
to place the ESD nmos to the snapback voltage?
In other words, the current will increase causing the vds too also
increase until it reaches the part in the curve where there is
negative resistance (2nd knee), at which point the Vds will snap back
to the Vsb voltage. Hence, during an ESD event the pad voltage will be
pulled back to Vsb.
Won't that place the device in a state from which it cannot exit ?
I mean that if the ESD current discharge stops when the mos device is
beyond the 2nd knee, won't the nmos be stuck at at voltage below Vbd?
I have trouble imagining that the Vds voltage will increase as the
current lowers in order for the nmos to go back to the origin of the I-
V curve.
Also, in order to reach the 1st knee of the curve, won't the esd mos
allow voltages to pass that are above the oxide breakdown voltage
(BVox), thus causing irreparable harm to any gates connected to that
pad ?
Any help will be appreciated.
Thank you
-Roger