MOS as switche.

MOS

Width + , Resistance - , Charge injection +
Width - , Resistance + , Charge injection - => Use paralle MOS, chip
area +

Fully-differential input, charge injection -, OP power + (than
single-end), chip area +, and need CMFB, chip area +.

High sampling clock, charge injection -, but, how high is high enough?

and is there any good method to simulate charge injection?


Thanks a lot!

Boki.