Terry Pinnell wrote...
Thanks. I thought at first that you must be saying there was a real
spike, and that this would remove it. But then I realised you meant
only the simulation.
Indeed - just tried it with the resistor, and it removes it. Can you
clarify what's happening here please?
.. ____
.. + --|D Q|---+---+--- timed pulse OUT
.. IN ----|> | | _|_ t = 0.7 RC
.. __ |__R_| R /_\
.. __/ |_____|___| diode that needs
.. | a series resistor
.. edge- C
.. trigger |
.. gnd
I have no idea why your simulation shows a spike, but in real life
the capacitor-discharge diode without a series resistor creates a
supply short on the Q pin at the oneshot-timeout flip-flop reset.
More accurately, it forces a full supply-voltage signal across
the logic-low-level Q output, causing a high current through the
ground pin of the CMOS logic IC until the capacitor is discharged.
A resistor added in series with the diode limits this current, and
only modestly decreases the maximum duty ratio the timer can handle.
BTW, in the drawing above I show the oneshot time** as t = 0.7 RC,
but actually this time ranges from 0.35 to 1.2 RC, because the CMOS
gate threshold Vt ranges from 30 to 70% of the supply voltage Vs.
Of course the RC value tolerances must also be considered. The very
poor accuracy of this circuit is one reason it's usually used only
for short non-critical time delays in a logic circuit (if the value
of C is much over 500pF, then a series resistor should be added to
the flip-flop's R terminal, as discussed elsewhere in this thread).
In contrast to the 4013 timer inaccuracy of +70% to -50%, the common
MC14538 oneshot inaccuracy spec is nearly 10x better, +6% to -8.6%
(at 10V). Clearly this is a much better CMOS part to use for timers.
** The timing formula is t = k R C, where k = ln (1 / (1 - Vt/Vs)).
If the threshold voltage is exactly 1/2 of the supply, then k is the
natural log of 2, or k = 0.69315 or 0.693, which is a number many of
us have memorized.
