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Mono from 1/2 x 4013

Discussion in 'Electronic Design' started by Terry Pinnell, Oct 3, 2004.

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  1. Anyone know how to make a mono from half a 4013 please?

    I've spent a while trying, but so far failed. I was pretty sure
    I'd done it a year or two ago, but darned if I can find anything, so
    maybe it was wishful thinking.
  2. Ken Smith

    Ken Smith Guest

    You feed the Q back to the R through an RC delay.
  3. A oneshot? D=1, clock as trigger input, R-C filter from Q to reset.
  4. Rolavine

    Rolavine Guest

    From: Terry Pinnell
    Well one way (I think) is to put D to VDD. clock the flop (mono) on a positive
    trans of the clk, feed the q output through a resistor to Res, and put reset
    through a cap to ground. You will also need a high value bleed resistor from
    res to ground.

  5. John Fields

    John Fields Guest


    | |
    | +-[<CR]-+ |
    +--+--+ | |
    Vcc>--------|D R Q|-+--[R]--+
    START>------|> | |
    | S | [C]
    +--+--+ |
    | |
  6. A bleed resistor adds nothing. An improvement is an extra diode as
    shown by John.
  7. Fred Bloggs

    Fred Bloggs Guest

    You use an RC-highpass as in the classical three-inverter oscillator:
    The timing k-factor is not particularly accurate ~1.8 assuming mid logic
    switching level IIRC:

    View in a fixed-width font such as Courier.

    | |
    | +----+-----+ T= k xRTxCT
    | | S,VDD | +----------+
    +--|D Q |-------+---> | |
    | | | | |
    | | \ | |
    +--- | 4013 | RT ---+ +--
    | | | \
    | | | /
    | >------|\ | |
    | |/ | CT |
    ---+ | _ | | | |
    | Q |--| |--+
    | | | | |
    | | |
    | R | |
    +----------+ |
    | |
  8. Fred Bloggs

    Fred Bloggs Guest

    Fred Bloggs wrote:

    Correction- R,S inactive low for 4000:
    View in a fixed-width font such as Courier.

    | |
    | +----+-----+ T= k xRTxCT
    | | VDD | +----------+
    +--|D Q |-------+---> | |
    | | | | |
    | , | \ | |
    +--- | 4013 | RT ---+ +--
    | | | \
    | | | /
    | >------|\ | |
    | |/ | CT |
    ---+ | _ | | | |
    | Q |--| |--+
    | | | | |
    | | |
    | S R | |
    +----------+ |
    | | |
    | +--/\/\----+
  9. John Fields

    John Fields Guest

  10. Thanks for all those. I'll try them tomorrow. Pleased to see I wasn't
    imagining it.
  11. Rich Grise

    Rich Grise Guest

    Not half as pleased as I am to see it's possible! ;-D ;-D ;-D

  12. Fred Bloggs wrote...
    Perhaps that's the way Fred does it (fixing the S-pin error), but the
    old-time experts did it just as Rolavine described, namely a direct
    connection to the flip-flop's reset pin. This approach is simple and
    straightforward and has the advantage of not forcing current into the
    CMOS chip's protection circuitry and substrate, a situation that has
    been known to introduce undesirable parasitic malfunctions into some
    IC chips.
    In this standard circuit the parameter k can vary from to 0.35 to 1.2
    according to the spec, a nearly 2:1 range from the nominal value as
    the threshold voltage varies from 0.3 to 0.7 of V+ (official spec).
    An early concern was the possibility of race conditions within the
    flip-flop, but the designs of each manufacturer's new version passed
    muster on this issue. Over many decades this circuit has worked well
    in production circuits creating functional pulses with non-critical
    time durations in hundreds of applications that I'm aware of, without
    trouble. (Side note: in practice the threshold variation range rarely
    reaches the common official wide 30 to 70% spec.)

    Fred's circuit doubles the voltage across the capacitor, which is why
    the time equation is longer. But it may well be more accurate against
    the threshold-voltage variation (if it doesn't completely malfunction),
    with k varying from 1.05 to 1.90 over the 30 to 70% threshold range,
    implying a 35% maximum variation from the nominal value. However, this
    analysis ignores the error introduced by the current flowing into the
    CMOS chip during the long overvoltage time through the third resistor.

    At any rate, anyone desiring an accurate delay time duration should use
    a CMOS oneshot chip or perhaps an honest digital time delay approach.
    The rest of us can use the standard simple two-part R-C circuit above.
  13. Fred Bloggs

    Fred Bloggs Guest

    Seriously, Win- this is exactly how the oscillator on the 4060 is
    configured- and the 4060 is fairly "old time" too. How far back are you
    going? The feedback is strongly positive all the way- and does not
    require any qualifying for race- it will work with any time delay.
  14. [/QUOTE]

    Just a data point Win. I had a customer who experienced
    unreliability (blown CMOS) with this sort of timing
    circuit. They were using Ct-values around 1uF and traced
    the problem to those occasions of power down when Ct was
    charged up. There was enough energy in Ct to destroy the
    input gate. A current limiting resistor in series with
    gate connection (R in this case) solved the problem.
  15. Fred Bloggs wrote...
    The vulnerability is no doubt the same now as it was decades ago. But
    seriously, it's not an issue I worry much about, for small substrate
    currents, but one does have to give it a bit of serious thought, even
    if in dismissal.

    In recent years here on s.e.d. we've been treated to claims by Jim and
    others that such substrate currents should be avoided as bad design,
    and we've been treated to several anecdotal examples of the undesirable
    effects this current has on other sections of an IC. We know that high
    currents, over 10 to 50mA, etc., can be serious trouble for an IC, even
    causing SCR latchup. We also know there can be crosstalk effects within
    the IC at lower currents. Unfortunately, no CMOS manufacturer has any
    specification for how high this current may be without effect. Perhaps
    this can account for the super-conservative position taken by some.

    At any rate, this does tend to make one more comfortable with circuits
    that have no such currents flowing under normal operation, as opposed
    to circuits performing the same function that do have such currents.
  16. Tony Williams wrote...
    This is a good data point. When the CMOS system is shutoff it's
    powered for a short while through the gate until the capacitor
    is discharged. The cases I'm familiar with have all used much
    smaller capacitors values, for short logic time delays, and have
    been battery applications that had low supply drains so the gate-
    powered condition was an innocuous one. Unless these conditions
    are met it'd be wise to add the resistor Tony suggests. However,
    unlike Fred's circuit, this resistor does not have any current
    flowing through it at any time during ordinary timing operation.
  17. I think everything conspired the other way in the case
    of that customer. High value caps, a topology that kept
    them charged to (a high) Vcc for most of the time, and
    a Vcc that went down quickly.
  18. Here's my successful result with the 'standard' circuit. I've only
    simulated, not breadboarded it, so do you reckon that 'spike' in the
    diode variation is real or an artifact of my simulation?

    Fred: I also tried your version, but the simulation failed with error
    "Float invalid operation exception". What's the suggested value of the
    lower R please? (I arbitrarily tried 1k, 10k and 100k, with same error
  19. Jim Thompson

    Jim Thompson Guest

    Improper simulation/use. What about the ESD structure on "R" ??

    ...Jim Thompson
  20. John Fields

    John Fields Guest

    I just wired it up and... no spike.

    Also, with a 0.47µF Mylar and 470k in there I get about 270ms.

    Interesting way to measure Vth of the RESET...
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