Connect with us

Mixing addres lines of SDRAM.

Discussion in 'Electronic Components' started by Wlad, Jul 9, 2004.

Scroll to continue with content
  1. Wlad

    Wlad Guest

    ear all,

    I have to boot-up a device based on Hitachi uP with external SDRAM
    (2x256Mb). The device was designed by somebody else and I only have to
    get it working. However there is something that bothers me very much.
    Probably to easen PCB layout the designer has mixed data and address
    lines for SDRAM: i.e. pin D0 of SDRAM is connected to pin D7 of uP. All
    other interface signals (RAS#,CAS#,CLK,CKE,UDQM,LDQM,WE#,CE#) are
    connected correctly. While mixing data lines seems ok to me (let me know
    if I'm wrong) mixing address lines looks unacceptable.
    Here are the connections:

    SDRAM uP
    A0 A5
    A1 A4
    A2 A3
    A3 A2
    A4 A14
    A5 A13
    A6 A12
    A7 A11
    A8 A10
    A9 A9
    A10 A6
    A11 A8
    A12 A7

    BA0 A15 (bank select)
    BA1 A16 (bank select)

    Will this connection work? For the time being I know that I must forget
    burst transfers. Are there any obstacles for SDRAM in this configuration
    to work with 1-byte burst transfers?

  2. Hello

    If this were SRAM then there will be no problem with the random connections
    as long as address is connected to address and data to data.

    If think that mixing up the data and address lines is a bad thing. I don't
    know much about SDRAM and therefore I read a data sheet about SDRAM.
    It looks like you only will be able to get one address at the time when the
    address lines are mixed.

    Mixing up the signals is a bad thing because if there were more items
    connected to the memory bus then it could give a lot of problems with the
    exact locations of the data structures.

    Could you tell which uP and which SDRAM chips there are used?

    If the uP can make burst transfer I will have asked the designer to redesign
    the circuit board because it's a bad design.

  3. While it might work, I'd be concerned about refresh...
  4. Tim Wescott

    Tim Wescott Guest

    Even if it was the boss?
  5. Bob Stephens

    Bob Stephens Guest

    Actually, as has been discussed several times here, address lines don't
    have to be in any particular order either. Now if you mixed data with
    address lines...

  6. Tim Wescott

    Tim Wescott Guest

    In the case of an SDRAM I beg to differ. The address lines are used to
    issue commands to the chip, and they aren't just randomly treated as
    addresses (at least on the one that I checked). Specifically the one I
    looked at assigns a special meaning to A10 which has nothing to do with
    where you want to read memory. See

    And even if it does basically work, as the OP pointed out it totally
    screws up burst reads, which on an SDRAM slows you down to a terrific
    degree (a factor of 8 or 10, IIRC).
  7. Bob Stephens

    Bob Stephens Guest

    Oops! That's what I get for not reading the OP carefully.

  8. Antti Lukats

    Antti Lukats Guest

    the hardware can not work! fire that somebody else if you can!
    addr bus *must* be connected properly to get the SDRAM to work.

  9. Hal Murray

    Hal Murray Guest

    I have to boot-up a device based on Hitachi uP with external SDRAM
    You have to read the fine print in the data sheets - both the
    memory chip and the CPU.

    Modern SDRAMs usually need some magic initialization commands.
    The "data" for that command is typically encoded on the address
    lines. Usually there is some magic firmware that does that.
    You may have to modify that - that is use a different address.

    I'd expect a CPU to read a whole cache block in burst mode.
    If you can't get it to avoid that you are probably out of luck.
  10. There is nothing wrong with mixing either type of lines. All it means is
    that addresses will not physically be at the expected addresses in RAM. It
    is more difficult to justify on a ROM, where programming in an external
    programmer will become 'hard'...
    Your address lines as listed, show A0, and A1 are not present from the
    micro. This means that four consecutive addresses, will all refer to the
    same memory cell. I'd assume from this, that there is actually a 4byte
    'latch'/multiplexor, and this is being used to select the individual
    'bytes' for the processor.

    Best Wishes
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day