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Microcontroller with external memory mapped peripherals

Discussion in 'Microcontrollers, Programming and IoT' started by rowan.bradley, Dec 15, 2013.

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  1. rowan.bradley

    rowan.bradley

    25
    1
    May 11, 2009
    I work on a system based on the 8051-family 80C320 processor. It has a 16 address bit 8 data bit bus, plus read/write etc. The IO is all memory mapped. I now want to replace or augment the processor with a new modern processor (an ARM or similar). I still need to use the existing memory mapped peripherals. Ideally I would buy a modern processor board (giving me USB, Ethernet, lots of memory, C compilers, a modern operating system maybe Linux, and if necessary video and sound output, keyboard and mouse input etc.) and interface it to the existing 8051 bus so I can still write to and read from the peripheral registers. Is this possible? What is the best way of designing it? Are some microcontrollers better than others at handling this type of IO? What sort of adapter circuitry would I need to connect the new micro to the old bus? Of course the new processor will be much faster than the old (which runs at 12MHz). I would rather use an off the shelf processor board for the new processor than design it from chips, since that should save a lot of work, and give me a working starting point.

    Ideally I would like to be able to read and write to peripheral addresses using a single instruction in the new processor. This (I think) rules out using GPIO pins for the address and data bus, because this would involve a lot of instructions just to do one read or write cycle.

    Thanks - Rowan
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    10,025
    2,138
    Nov 17, 2011
    The question can be answered in detail only if one knows which processor is going to be used.
    Apart from that, any parallel bus that is suitable to control standard SRAM is basically suitable to control old 8051 peripherals. You will need a memory controller (in the new µC) that allows progarmmable length of bus cycles or that allows to extend a bus cycle by an external signal (ready or similar) to adapt the bus speed to the old chips when accessing them. You may also need to adapt the timing of the control signals (read/write, CS). If you can do it by a programmable memory controler, fine. If not, you will need external logic.
    You will also have to observe the byte order (or endianness) when conecting old peripherals to the new bus.

    All in al, it is feasible, but I would recomend to switch to new hardware completely. Or keep the old µC system completely as an intelligent subsystem and comunicate from the new processor to the old subsystem via e.g. a serial interface. I know that goes against the "single instruction" idea, but generates probably the least hassle.
     
  3. rowan.bradley

    rowan.bradley

    25
    1
    May 11, 2009
    Thanks for your reply.

    I will choose a processor that has all the necessary features _and_ has this ability to read and write from the old peripherals. Preferably I would like to be able to buy a processor board with the right chip on it together with USB, ethernet etc., to avoid the need to design a multilayer SMD board. But it absolutely has to have the external peripheral interfacing capability.

    I understand your suggestion to keep the old processor, but before I opt for that solution, it seems that I ought at least to know how elegant a solution could be developed using the other way (new processor linked to the old bus). Then at least I'm comparing the pros and cons of two known solutions, rather than comparing a known one with a fuzzy concept that I haven't been able to give any form to.

    It seems that the TI Stellaris M3 processors had something called External Peripheral Interface (EPI) which is more or less exactly what I need. It even had some nice features (e.g a FIFO, and an non-blocking read instruction) to handle the difference in timing between the new and old systems. Unfortunately all the M3 processors are marked Not Recommended for New Designs, and the M4 processors do not have this EPI feature.

    Does anyone know of a modern processor which has an external address-and-data bus of this sort?

    Thanks - Rowan
     
  4. gorgon

    gorgon

    603
    24
    Jun 6, 2011
    The Freescale Kinetis series has several variants of external memory interface, and is relative new.
    The STM STR9xx series also has the external memory interface, but I don't know how they are placed on the 'chip life cycle'.

    If you plan to use existing memory mapped hardware, you should also be aware of the possibility of interface problems between 3.3V and 5V logic. You may need level shifter buffers.
     
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