As the 80386 is a 32 bit system an the address lines addres words (32 bit = 4 byte) this seems correct.
one 1024 MB can be addressed by 30 address lines, so three 1024 can be addressed with 32 address lines
1024 MB requires 30 address lines for bytewise addressing. If the memory were addressed wordwise, not bytewise, then you'd use less address lines. In this contect, 30 seems correct.
for a 512 MB ........stuck from here
No need to get stuck. 512 MB = 1/2 * 1024MB. What does this mean in terms of address lines?
Once you have figured this out, you can proceed to the next part of the task:
Design a logic circuit to address three 1024 MB RAMs and two 512 MB RAMs .
The 80386 doesn't know about memory chip sizes. You'll have to devise a way to create chip select signals for the single memory chips from the address lines. Hint: look for address decoder...
Once you have the parts together, it is a good idea to draw a block diagram to show how the components interact. Similar to this
example for an 8085 system (you'll need to modify this to a large extend to match the 80386's 32 bit bus and the memory structure required as per the task description above).
