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Meaning of "dynamic clock"?

Discussion in 'Electronic Design' started by Tim Williams, Jan 3, 2009.

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  1. Tim Williams

    Tim Williams Guest

    What does it mean when a processor has a dynamic clock? 8086 for instance.

    I notice, also, that many chips are (or were) available in HMOS and CMOS,
    and the CMOS versions were static (could be clocked arbitrarily slowly).
    Why the difference?

    Also, what happens when you clock something too slow? Does it start
    skipping beats? Does it lose data (internal dynamic RAM perhaps?)? I
    presume the clock is capacitively coupled somewhere for some reason, which
    suggests differentiator action, and therefore won't work very well,
    principally to asynchronous signals I suppose.

    Tim
     
  2. krw

    krw Guest

    It could mean several things, but in this case I'd take it to mean the
    device used dynamic (or Domino) logic. Basically, once a cycle the
    state of a node is forced to say '1'. Later in the "cycle" if an
    event occured the node was pulled to a '0'. If the event didn't
    occur, the '1' remained. Now string these together (alternating '1's
    and '0's as the "precharge" state). It is dynamic because the vaue is
    stored on the node's capacitance.

    http://en.wikipedia.org/wiki/Domino_logic
    See above. The value of the internal nodes is stored on a capacitor,
    which leaks. P/NMOS designs used dynamic logic pretty much
    exclusively. CMOS can be made "static" (all state held on full
    latches, domino logic is still present in many CMOS designs for
    space/speed reasons. These designs will also have a minimum clock
    rate.
    Yes, though it's dynamic logic internal to the device.
    No, not the clock and not capacitively coupled or differentiators of
    any kind. The data is stored on (parasitic) capacitors rather than
    using full latches.
     
  3. Guest

    Dynamic logic saves components too in CMOS. You don't need all those P
    devices to mirror the N devices. I'm not sure I'd consider it old, if
    by that you mean, it isn't used anymore.
     
  4. krw

    krw Guest

    VLSI CMOS is usually *not* static. Very few high end microprocessors
    are fully static and usually do contain at least some domino logic.
    It's faster, smaller, and uses less power than a fully static design.
     
  5. krw

    krw Guest

    Right, because the benefits of domino logic dont' matter to N-10
    technology. FPGAs pretty much have to be static. The tools are a
    nightmare even with static logic..
    Products that are not on the bleeding edge tend not to use bleeding
    edge design techniques, no.
     
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