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master-slave flip flop vs edge triggered flip flop.

Discussion in 'Electronic Design' started by Spehro Pefhany, May 28, 2008.

  1. Guest

    hi all,
    I want to know the advantages of edge triggered flip flop over master-
    slave flip flop.
    Please let me know this.
    thanks in advance.
     
  2. MooseFET

    MooseFET Guest


    It is politically incorrect to have one flip-flop be a slave to
    another so you can keep yourself out of trouble by calling them edge
    triggered.
     
  3. MooseFET

    MooseFET Guest

    Not if resistors, capacitors, and inductors are involved in the input
    section. The first stage is a half shot not a flip flop.
     
  4. Guest

    Hi all,
    Thanks for answers.
    Sorry I will reframe my Question.

    " advantages of edge triggered flip flop over master-
    slave Latch set up"

    thanks in advance..
     
  5. Technically you're right. But is is also politically incorrect to go too
    deep into this question.
    (Too deep is beyond the point that politicians can or will understand.:)

    petrus bitbyter
     
  6. MooseFET

    MooseFET Guest

    I was refering to a MML[1] flip-flop design.

    Posting it in ascii art is a little beyond what I'm willing to do but
    I will give you the input section from memory:


    22p !/
    Clock ----!!------+------+-----!
    ! ! !\e
    330R \ --- !
    / ^ 0v
    \ !
    ! 0v
    )
    22u )
    )
    !
    0V






    [1] MML = Mickey Mouse Logic
     
  7. Rich Grise

    Rich Grise Guest

    http://www.learn-c.com/74ls74.pdf

    Page 4.

    Cheers!
    Rich
     
  8. Tim Williams

    Tim Williams Guest

  9. I know, I know. But as I wanted to stay politically correct I could not say
    so :)

    petrus bitbyter
     
  10. krw

    krw Guest

    He's already won everywhere else.
    Air America is some piece of work, eh?
     
  11. Paul

    Paul Guest

    I ran into this dilemma when using 74LS76's and 74LS76A's for a
    student lab. The TI datasheet is at:
    www.df.unipi.it/~flaminio/laboratori/pdf_files/SN7476.pdf
    This chip comes in two versions, master-slave (74LS76), and
    negative edge triggered 74LS76A).
    The description at the beginning tells you that when the clock is
    high, J.K inputs are loaded into the master. On the high-low
    transition the outputs are transferred to the slave.
    The end result is that your data must be stable for while the clock
    is high (master-slave version), whereas it must be stable for one
    "setup time" (20ns for 74LS76A) before the negative clock transition.
    Most people would want the edge triggered version, keeping inputs
    stable while clock is high (master-slave) would be more of a pain.

    -Paul
     
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