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manually operated 2 digit up/down counter

Discussion in 'Electronic Design' started by scarlet, Aug 1, 2005.

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  1. scarlet

    scarlet Guest

    Hi,

    I need to build a 2 digit (00-99) up/down counter.

    the system must have an "count up" button and a "count down" button.

    when the "count up" button is pressed the counter must add 1 tot it's
    current amount
    similar for "count down" ...

    somebody is operating the count up, and someone else is operating the count
    down button, to monitor a production process. Every time an order comes in,
    a person presses the "count up" button. someone else produces the order, and
    when ready presses the "count down" button

    this way everyone can see how many more oders are "pending" ...

    I'm sure there is a simple solution for this, but I haven't found it yet

    Please help

    Thanks

    Pascal

    P.S. To reply, remove the "+" from the Email adress
     
  2. Ken Taylor

    Ken Taylor Guest

    Search for "up/down counter", or check out PIC's.

    Ken
     
  3. I'm with "Telecom" on this one.


    Best regards,
    Spehro Pefhany
     
  4. samIam

    samIam Guest

    I need to build a 2 digit (00-99) up/down counter.

    This project screams "synchronous binary counter" aka
    state machine.

    You can implement that easily within one PALx chip. Probably a
    22v10 considering the number of outputs youd need
     
  5. DaveM

    DaveM Guest


    Check out the datasheets for the CD4029 presettable Up/Down counter, and the
    CD4056 BCD-7 segment decoder-driver. They will do what you need, in
    addition to giving you the ability to preset a count into the counters.
    You'll need additional logic to prevent the count from going from 00 to 99
    in case of a down command when the count is at 00.
    Alternatively, a PIC is a very good choice here, but requires a bit of
    coding to be done. Do whichever is more comfortable for you

    --
    Dave M
    MasonDG44 at comcast dot net (Just subsitute the appropriate characters in
    the address)

    Never take a laxative and a sleeping pill at the same time!!
     
  6. Jim Thompson

    Jim Thompson Guest

    Surf on 'BCD "up down counter"'

    ...Jim Thompson
     
  7. Ken Taylor

    Ken Taylor Guest

    Don't tell me you actually *read* the book? :)

    Ken
     
  8. Ben Bradley

    Ben Bradley Guest

    Get an old 386/486 machine running MS-DOS (used to be a few dollars
    at any thrift store but I think they quit accepting computers this
    old) and write a quickbasic program to do this function. Have one key
    be "count up" and another key be "count down."
     
  9. Clive Tobin

    Clive Tobin Guest

    To heck with PICs and programming and incomprehensible instructions, or
    using a whole big computer!

    I suggest using a couple of CD40110BE ICs which are exactly what you
    want, they are cascadable up-down decade counters with separate up and
    down inputs, with 7-segment decoder-driver built in. They are not so
    popular any more but TI still makes them and Digi-Key has zillions
    (hundreds, anyway) in stock at about $1 each.

    You need resistors to limit the current to the CC readouts, and you
    might need a bounceless pushbutton circuit on the inputs. The latter
    can be made with an SPDT switch and cross-coupled CMOS inverters, with
    no other parts needed. You also need a Reset button or else power-on
    reset.
     
  10. Sure did, pretty much in one sitting. I always wonder what interesting
    stuff the author might have left out for whatever reasons, but that's
    another story. ;-) Thanks for the pointer.

    For the OP:

    Here's a slightly arcane fragment of midrange PIC code from Dimitry
    Kiryashov for increment of a packed BCD number (the PIC does not have
    a decimal adjust instruction so you have to write code to correct
    using the DC (digit carry) flag): reg is some arbitrary byte in the
    current ram bank.

    incf reg,F
    movlw 0x66
    addwf reg,F
    skpndc
    andlw 0xF0
    skpnc
    andlw 0x0F
    subwf reg,F

    The zero flag is valid at the end so you can use that to indicate when
    a carry should take place if you have multiple bytes

    And for decrement:

    movlw 0x01
    subwf reg,W
    skpdc
    xorlw 0x06
    skpc
    xorlw 0x60
    movwf reg


    Best regards,
    Spehro Pefhany
     
  11. Fred Bloggs

    Fred Bloggs Guest

    The 40110 idea seems best, and the circuit would look something like this:
    View in a fixed-width font such as Courier.


    common
    cathode
    +-CD40110B-+ +---------+
    --- | | | |
    +---o o-+ +---------|RST a|-R---| |
    | sw1 | UP | | | | a |
    | | +---+ | | b|-R---| --- |
    | +--|OS1|---|--------->CKUP | | | | |
    | +---+ | | c|-R---| f| |b |
    | +---+ | | | | --- |
    | +--|OS2|---|--------->CKDN d|-R---| e| g | |
    | | +---+ | | | | | |c |
    | --- | DWN | |___ e|-R---| --- |
    +---o o-+ | +----|TEN | | d |
    | sw2 | | | f|-R---| |
    --- | | | | | |
    /// | +----|LEN g|-R---| |
    | | | | +----+----+
    | --- | | |
    | /// |BRW CRY | ---
    | +----------+ ///
    | | |
    | | |
    VDD | +-------+ |
    | | | |
    | --- | | +---------+
    +---o o---+ | | common
    sw3 | | | cathode
    | | | +-CD40110B-+ +---------+
    +---+ | | | | | | |
    +--|OS3|--+---------|RST a|-R---| |
    | +---+ | | | | | a |
    | RST | | | b|-R---| --- |
    | | +-->CKUP | | | | |
    | | | c|-R---| f| |b |
    | | | | | --- |
    | +----->CKDN d|-R---| e| g | |
    | | | | | |c |
    | |___ e|-R---| --- |
    | +-----|TEN | | d |
    | | | f|-R---| |
    | | | | | |
    | +-----|LEN g|-R---| |
    | | | | +----+----+
    | --- | | |
    | /// |BRW CRY | ---
    | +----------+ ///
    | |
    | |
    +---------------------+




    SW1 UP COUNT MOMENTARY NORMALLY OPEN

    SW2 DOWN COUNT MOMENTARY NORMALLY OPEN

    SW3 RESET MOMENTARY NORMALLY OPEN

    OS1,OS2 DEBOUNCE ONE-SHOTS

    OS3 RESET ONE-SHOT




    OS1,OS2 DEBOUNCE ONE-SHOT CKTS (2)


    VDD
    |
    +---------+---+
    | | |
    | +------------LM555
    [100K] | VDD RST |
    | | |
    | | |
    | | OUT |-----> output
    from >--[470]---+---|THRESH |
    switch | | |
    +---|TRIG DIS |
    | | |
    | | CON |
    | | |
    === | GND |
    0.47U| +---------------+
    | |
    | |
    +-----------+
    |
    ---
    ///








    OS3 RESET ONE-SHOT CKT


    +----------+
    | |
    --- |
    /// +-------CD4013
    | SET |
    | |
    VDD>----|D Q|------+--[10K]--> output
    | | |
    | | [100K]
    from >---------->CK | |
    BRW | _| |
    | Q|--||--+
    | RST | 0.1U |
    +-----------+ |
    | |
    | |
    +---[1M]-----+


    +---------+
    | |
    | +-------CD4013
    | | SET |
    | | |
    +---|D Q|-
    | | |
    | | |
    +--->CK |
    | | _|
    | | Q|-
    | | RST |
    | +-----------+
    | |
    +---------+
    |
     
  12. Ken Taylor

    Ken Taylor Guest

    Glad you enjoyed it. We had a great time on the island, and I had a lot of
    fun rebuilding a telco. I'm off to Pitcairn Island in a few weeks to look at
    their infrastructure - fun in the sun! :)

    Anyhoo, many moons ago I built a chess timer based on one of the 74C92x
    family (I forget which one now), which is essentially the same idea. However
    by the time you put all the glue bits next to any of these 74xxx family
    chips to get a display counter going, you may as well use a PIC which can
    then do 'other stuff' as it is required (and it will be).

    One thing I'd be dubious about in an application such as the OP is looking
    at is what happens when both orderer and picker push a button at the same
    time, or maybe you want to have several people doing either or each task and
    therefore increase the risk of simultaneous events. Having done a much
    larger system (full inventory tracking as well as pick-list functionality),
    I can appreciate the need for an orderly and predictable handling of such
    events..

    Cheers.

    Ken
     
  13. Fred Bloggs

    Fred Bloggs Guest

    In the extremely unlikely event the orderer and picker press their
    switches within 0.0000001 seconds of each other, the result will be that
    a count *may* not register for one of them but not both. Both users have
    visual feedback by way of the display, so that the orderer is expecting
    either an increment or stay the same, and a lost count would mean he/she
    sees a decrement. My, my, my, ooh and ahhh, what a catastrophe, he/she
    merely re-presses the momentary. The case of picker expecting either
    decrement or stay the same seeing an increment is likewise the same.
    Ehhh big deal- then each switch registers with a task latch that is
    sequentially serviced by a simple scan circuit and cleared afterwards-
    nothing insurmountable there.
    IOW, something that is conceptually simple....
     
  14. .... becomes yet another microcontroller project. ;)

    Jon
     
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