# manipulate voltage output in transimpedance amp circuit

Discussion in 'General Electronics Discussion' started by robismyname, Jan 30, 2013.

1. ### robismyname

5
0
May 22, 2012
I have a circuit (attached) that is providing too much voltage into my FPGA. I attached the circuit.

The output of the transimpedance amp (OPA380) is sending 4.2V to my FPGA which only needs 3V. I have reason to believe that the 4.2V input into the FPGA is causing some weird anomalies to occur while testing my FPGA with 4.2V input from amp. I was wondering if I increase the voltage drop at R80 would that help bring the voltage down to 3V into my FPGA. Or is the voltage output controlled by both R80 and R78?

Basically I need to know how to get my voltage output to 3V instead of 4.2V. Circuit is attached.

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2. ### Laplace

1,252
184
Apr 4, 2010
In this transimpedance configuration the output voltage is controlled by the current flowing into pin J25-3 from R78. With no current the output voltage should be zero. All the current that flows into J25-3 comes through R78, and that V=IR voltage drop across the resistor becomes the output voltage.

So to lower the output voltage you can do one or all of the following:

1- Reduce the current sourced by whatever is attached to the left of J25-3.
2- Reduce the value of R78 to lower the voltage drop.
3- Add a resistor in parallel with C128 to form a voltage divider with R80.

3. ### (*steve*)¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥdModerator

25,496
2,837
Jan 21, 2010
A voltage divider would probably be better. something like a 330 ohm resistor and a 680 ohm resistor in series from the input to ground, with the junction connected to the FPGA.

The 680 ohm resistor is connected to ground.

This will give you 2.9 volts, and that may be close enough. If you require something closer, 220R and 560R give you 3.02 volts (but with lower impedance presented to your op-amp).

edit: ignore me, I was assuming the device shown was the FPGA, not the op-amp.

4. ### robismyname

5
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May 22, 2012
The input is is coming in from the left side J25 pos 3. Th input is current. The current goes to pin 2.

The off page connector called SER_IN is really the input signal going to the FPGA. SER_IN is what is coming out of the AMP.

I didnt measure the current coming in to pin 2 but I know the source voltage is 10 V and there is a 5K ohm resistor in series with pin 3 of J25 so that current is provided to the AMP pin 2 as it needs in order to work. I was thinking about placing a 2200R to the right side of R80 to make a voltage divider. I think that will get me about 3V.

What is the 200K and c125 47pF doing in the circuit?

5. ### robismyname

5
0
May 22, 2012
Does any of your answers change if the input is is coming in from the left side J25 pos 3?The input from J25 pos 3 is current. The current goes to pin 2.

The off page connector called SER_IN is really the input signal going to the FPGA. SER_IN is what is coming out of the AMP.

I didnt measure the current coming in to pin 2 but I know the source voltage is 10 V and there is a 5K ohm resistor in series with pin 3 of J25 so that current is provided to the AMP pin 2 as it needs in order to work. I was thinking about placing a 2200R to the right side of R80 to make a voltage divider. I think that will get me about 3V.

What is the 200K and c125 47pF doing in the circuit again?

25,496
2,837
Jan 21, 2010

7. ### robismyname

5
0
May 22, 2012
When a resistor is in parallel with C128 how does the capacitor contribute to the voltage across the resistor?

8. ### Laplace

1,252
184
Apr 4, 2010
C128 in combination with the output resistor forms a low-pass filter by shunting higher frequency signals to ground. According to Thevenin's Theorem, placing a resistor across C128 will decrease the equivalent resistance driving the capacitor thereby raising the corner frequency of the low-pass filter. The capacitor only has an effect during signal transitions.