Main memory <-> Cpu communication ?

[Skybuck Flying]

Hi,

I think pentium's and athlon cpu's work as follows with main memory:

CPU <--- 32 bit bus ---> Main Memory
or
CPU <--- 64 bit bus ---> Main Memory

See bits are retrieved from main memory in parallel.

However... suppose two 32 bit integers have to be read, added together, and
written back.

Does this mean that it works like this ?:

CPU <--- read 32 bit integer A ---- Main Memory
CPU <--- read 32 bit integer B ---- Main Memory
CPU ----- write 32 bit integer C ---> Main Memory

( C would be impossible on pentium/athlon since it has to be added to A...
but I dont want that...
I won't to directly write to C A must remain intact as well as B )

Now the following question:

Suppose I want to read and write 1.000.000 bits.

This would mean it would look like this ?:

CPU <--- read 32 bit integer A ---- Main Memory
CPU <--- read 32 bit integer B ---- Main Memory
CPU ----- write 32 bit integer C ---> Main Memory

CPU <--- read 32 bit integer A ---- Main Memory
CPU <--- read 32 bit integer B ---- Main Memory
CPU ----- write 32 bit integer C ---> Main Memory

CPU <--- read 32 bit integer A---- Main Memory
CPU <--- read 32 bit integer B ---- Main Memory
CPU ----- write 32 bit integer C ---> Main Memory

CPU <--- read 32 bit integer A---- Main Memory
CPU <--- read 32 bit integer B ---- Main Memory
CPU ----- write 32 bit integer C ---> Main Memory

etc.

This could mean that after the read is done... the bus is idling... so it's
not used ? etc... and while writing it's idling as well ?

Wouldn't a single/variable bit cpu with serial communication wires with main
memory be faster in this case ???

CPU <---- read bitstream A -------- Main Memory
CPU <---- read bitstream B -------- Main Memory
CPU -----> write bitstream C -----> Main Memory.

In this case the "bus" is more efficiently used... it's constantly busy...
it's constantly transferring bits across the wire...
It doesn't have to wait so much

Only 3 wires have to be used as well... so multiple cpu's could be doing
other things in parallel

Bye,
Skybuck.

 

[Patrick Schaaf]

[intel/amd processors, presumably x86]

Does this mean that it works like this ?:

CPU <--- read 32 bit integer A ---- Main Memory
CPU <--- read 32 bit integer B ---- Main Memory
CPU ----- write 32 bit integer C ---> Main Memory

No. It usually works like this: the CPU transfers (reads or writes)
a whole cache line, 32 or 64 or 128 BYTE, between CPU caches and
main memory.

Everything else happens inside the CPU.

best regards
Patrick

 

[Jonathan Kirwan]

I think pentium's and athlon cpu's work as follows with main memory:

CPU <--- 32 bit bus ---> Main Memory
or
CPU <--- 64 bit bus ---> Main Memory

See bits are retrieved from main memory in parallel.
<snip>

For PPro and Pentium II, the front side bus uses (4) 8-byte wide data
transactions as part of a 7-cycle transaction composed of: (1) the
transaction cycle, (2) the error cycle, (3) the cache hit cycle, (4)
data line 1, (5) data line 2, (6) data line 3, and (7) data line 4.
The current transaction, the prior error cycle, the cache hit before
that, and an even earlier data line can all operate in parallel.

Each of the chips attached to the front side bus maintain a queue of
up to 8 pending transactions, yet to be satisfied. There are inbound
and outbound queues in the chipset, read-around-writes, etc. It helps
in making effective use of the resources.

Jon