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LVS in cascode ..it seems to match but :(

Discussion in 'Electronic Design' started by Matteo, Jun 4, 2007.

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  1. Matteo

    Matteo Guest

    hi all!
    as someone of you knows, I'm trying to project a cascode amplifier by
    myself. I finished the schematic and now I'm working on the layout
    (never done before, God save me please..)


    here is my schematic:
    http://www.thebags.it/listing/layout/01/schem.png


    here is the entire layout I designed
    http://www.thebags.it/listing/layout/01/layout_tutto.png

    and some relevant particulars:

    - M1 and IN1
    http://www.thebags.it/listing/layout/01/M1.png

    - connection between M1 and M0 and IN0
    http://www.thebags.it/listing/layout/01/conn_m1_m0.png

    - connection between M0 and the resistance connected to vdd
    http://www.thebags.it/listing/layout/01/resistance_m0.png

    (Do you think my layout should match the schematic? take a look to the
    pins ..I'm not sure they are ok)


    1.: I run VRC and it sad only something about the density of my MET1 and
    POLY1 areas ..I didn't care ..hope I was right

    2.:Then I extracted the circuit and run LVS ..LVS does not recongnise
    that I mad my MOS with 13 gates instead of one and give me some errors
    about it. Then there are some errors I'm not able to understand ..here
    it is:

    ######START

    @(#)$CDS: LVS.exe version 5.1.0 07/02/2006 21:13 (cicln01) $

    Command line: /nfsd/iccad/cds/ic5141b/tools/dfII/bin/32bit/LVS.exe -dir
    /home/bassimat/CAD/LVS -l -s -t /home/bassimat/CAD/LVS/layout
    /home/bassimat/CAD/LVS/schematic
    Like matching is enabled.
    Net swapping is enabled.
    Using terminal names as correspondence points.

    Net-list summary for /home/bassimat/CAD/LVS/layout/netlist
    count
    6 nets
    5 terminals
    26 nmos4
    1 rpoly2

    Net-list summary for /home/bassimat/CAD/LVS/schematic/netlist
    count
    6 nets
    5 terminals
    2 nmos4
    1 rpoly2


    Terminal correspondence points
    N0 N2 IN0
    N4 N7 IN1
    N3 N6 OUT
    N2 N1 gnd!
    N1 N0 vdd!

    Devices in the netlist but not in the rules:
    nmos4 pcapacitor rpoly2

    Ill-defined correspondence points.

    N0 N2 Accepted because one is a subset of the other
    N3 N6 Accepted because one is a subset of the other
    N4 N7 Accepted because one is a subset of the other
    N2 N1 Accepted because one is a subset of the other
    N2 N1 Accepted because one is a subset of the other
    N0 N2 Accepted because one is a subset of the other
    N3 N6 Accepted because one is a subset of the other
    N4 N7 Accepted because one is a subset of the other


    Device summary for layout
    bad total
    nmos4 26 26


    Device summary for schematic
    bad total
    nmos4 2 2

    The net-lists failed to match.

    layout schematic
    instances
    un-matched 26 2
    rewired 0 0
    size errors 0 0
    pruned 0 0
    active 27 3
    total 27 3

    nets
    un-matched 1 1
    merged 0 0
    pruned 0 0
    active 6 6
    total 6 6

    terminals
    un-matched 0 0
    matched but
    different type 0 0
    total 5 5


    Probe files from /home/bassimat/CAD/LVS/schematic

    devbad.out:
    I /MN1
    ? Device does not cross-match.
    I /MN0
    ? Device does not cross-match.

    netbad.out:
    N /net14
    ? Net does not cross-match. It has 2 connections.

    mergenet.out:

    termbad.out:

    prunenet.out:

    prunedev.out:

    audit.out:


    Probe files from /home/bassimat/CAD/LVS/layout

    devbad.out:
    The no. of lines exceeded than specified by the variable
    lvsLimitLinesInOutFile.
    To see the complete information please see the file:
    /home/bassimat/CAD/LVS/layout/devbad.out

    netbad.out:
    N /6
    ? Net does not cross-match. It has 26 connections.

    mergenet.out:

    termbad.out:

    prunenet.out:

    prunedev.out:

    audit.out:

    ######END


    I run a simulation on the extracted circuit but the result is horrible
    ...it's another circuit :(

    can give me some suggestion about my layout? am I making some big mistakes?

    thank you all!

    matteo
     
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