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LVPECL to 3.3V CMOS Levels

Discussion in 'Electronic Design' started by pfitz, Nov 7, 2003.

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  1. pfitz

    pfitz Guest

    Hi all,

    I'm designing a PLL which will give an output frequency of 155.52MHz in
    LVPECL. I was wondering if anyone knew the best way to convert this to CMOS
    for my Phase Detector.

    are there dedicated LVPECL to CMOS chips out there and are they expensive?

    Or is there a cheaper way of doing this perhaps with a High frequency

    bearing in mind that I don't care what the output looks like as long as it
    crosses the CMOS thresholds.



  2. Fred Bloggs

    Fred Bloggs Guest

    Which phase detector are you using?
  3. You shouldn't consider 155MHz for CMOS. Way too high.
    Use a differential input phase detector.
    BTW, there are PLL chips, that do everything for you.

  4. Jim Thompson

    Jim Thompson Guest

    Yes available, cost I don't know, try:

    ...Jim Thompson
  5. pfitz

    pfitz Guest

    Just using a digital phase detector in a (xilinx) CPLD, the outputs of which
    will drive an Analog Filter.

    I realise the frequency is rather high for CMOS but if the tracks are kept
    short would that still be such a problem.

    I mean when you have CPUs with front side busses of 133Mhz and above, surely
    they must be converted to CMOS, no?

  6. John Larkin

    John Larkin Guest

    OnSemi, maybe Synergy too, has these. Look at the 10ELT parts. They
    are a bit slow, in my experience.
    An fast opamp would work, but that's probably overkill. Cooler would
    be a 3.3v CMOS LVDS line receiver, like one of the National or TI
    parts. They are cheap and blindingly fast, and should work directly
    with the LVPECL, or maybe with a small level shift, easily done with a
    couple of R-Cs in the pecl pulldowns.
    Would you object to a near-perfect square wave?

  7. John Larkin

    John Larkin Guest

    Not any more. You can buy 400 MHz cmos LVDS parts, and I'm now using a
    Tiny Logic flipflop with 1 ns typ Tpd; that's as fast as 10KH ECL.

    Aren't Pentiums scheduled to clock at 10 GHz in a couple of years?

  8. John Larkin

    John Larkin Guest

    Their ecl/ttl converter (10ELT21? I forget) is a cmos part, and it's
    actually a lot better than the Moto/OnSemi equivalent, which uses some
    old MosaicII or somesuch bipolar process and has weird jitter issues.

  9. Jim Thompson

    Jim Thompson Guest

    Yep, I like their parts... I've done a *lot* of design work for
    Arizona Microtek ;-)

    They're in Mesa, AZ.

    ...Jim Thompson

  10. I too measured a risetime of 450ps on an CMOS output of an FPGA,
    however this signal is not meant to be routed as no impedance
    is given. Those signals meant to be routed are usually
    differential at that speed and an impedance is specified.

  11. John Larkin

    John Larkin Guest

    They are very nice people. I talked to the Prez (Harold?) about my
    ELT21 problem, sent him scope shots of the Moto jitter, and got
    samples with his hand-scrawled note; what's the chances of my being
    able to talk to the president of Motorola?

    Buy their stuff! It's good!

  12. Jim Thompson

    Jim Thompson Guest

    Yep, I've been working with Harold Muller for close to 20 years.

    ...Jim Thompson
  13. Mac

    Mac Guest

    Those busses use some pretty fancy schemes to maintain signal integrity.
    They have termination resistors which pull to a termination voltage
    (typically half the signalling voltage) and they have a switch threshold
    input that is supposed to be held at that same termination voltage.

    But If the CPLD seems to be spec'd to work at the speeds you are
    proposing, you should be alright.

    I would recommend that you put a series resistor near the source, and a
    shunt capacitor near the load. You can always use a zero-ohm resistor and
    leave the capacitor unpopulated, but if you need them later and the pads
    aren't there, then you'll be out of luck.
    You've already got a couple of suggestions. I'll just point out that you
    could probably use almost any differential receiver spec'd for 3.3 volt
    operation and ( the right switching speed). For example, an LVDS
    transceiver might work. You just have to make sure you respect the common
    mode voltages.

    I wouldn't use an op-amp. Generally, all the things that make op-amps good
    op-amps make them lousy high speed logic chips. But there are a lot of
    high-speed comparators that might do the job.


  14. Fred Bloggs

    Fred Bloggs Guest

    This is a straightforward LVECL->LVCMOS and can be done typically up to
    350MHz. The most readily available part will be the ONSemi MC100EPT23 at
    $8/ea small quantity. Others are the Micrel SY100EPT23L and SY89323L,
    and ICST ICS83023I.
  15. expensive?

    Lots of expensive parts. But they work and you don't have to do much
    "analog" design.
    How about "MECL SYSTEM DESIGN HANDBOOK" pg 212 Fig 9b ?
    If you use a PNP like BFT92 for the 2N3906 and maybe do some level
    shifting for the differential ECL signals / output signal you should be
    able to cheaply do it. And maybe some termination at the CMOS receiving
    I managed to convert 3ns wide pulses and process them in a CMOS ASIC
    this way.

    Raymund Hofmann
  16. Fred Bloggs

    Fred Bloggs Guest

    You're welcome to firm up that design using a single 3.3V/GND power
  17. John Larkin

    John Larkin Guest

    The newish Xilinx chips accept differential inputs, including LVPECL,

    But how about this: AC couple the sig into fpga pin1, invert
    internally, bring that out pin2, and feed back through a largish
    resistor to the cap/pin1 node. This servoes the DC bias level, at
    which point 0.8 v p-p is lots of swing.

  18. That would be be pfitz job.
    But Before doing this, he could try to use some ready made RF
    transformer for the job, as it seems to be no DC.

    Raymund Hofmann
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