LTspice demonstrate Delay Function in Flyback Converter

Demonstration to be posted to the binaries newsgroup later on.

I'd always been dissapointed in my attempt to model and compensate
flyback converters and some other examples of SMPS feedback loops and a
while back began to consider the possibility that there was some sort of
delay function in the loop.

My attempts with TINA indicated that this might be valid but I couldn't
decide which was the correct delay. I couldn't get TINA to hack things
with its delay block.... didn't try it with a transmission line though.

I've just returned to the problem using LTspice and implemented the
delay with a transmission line. This is for a discontinuous mode flyback
and the results are quite sweet. They indicate that the delay is there
and is equal to the switch duty cycle. The results probably apply to
continuous mode operation as well.

The point is verified by running a linear model in tandem with the
switching model.

I'll post the .asc file to the binaries group later on today and, when I
get around to it, deal with it more exhaustively on my website.

DNA

http://genome.dna.tripod.com/index.htm

 

Delays are always a element in sampled systems. You can't correct for
something before you know what it is. A switch mode supply won't give you an
indication of what the output voltage is until after the switch cycle is
complete. In effect, it's a sampled system with all that implies.

Jim

 

| On Sat, 3 Apr 2004 15:16:17 +0100, "Genome" <>
posted this:
|
| >
| >I've just returned to the problem using LTspice and implemented the
| >delay with a transmission line. This is for a discontinuous mode
flyback
| >and the results are quite sweet. They indicate that the delay is
there
| >and is equal to the switch duty cycle. The results probably apply to
| >continuous mode operation as well.
| >
| >DNA
|
| Delays are always a element in sampled systems. You can't correct for
| something before you know what it is. A switch mode supply won't give
you an
| indication of what the output voltage is until after the switch cycle
is
| complete. In effect, it's a sampled system with all that implies.
|
| Jim
|
|

Not true for buck and buck derived converters. The switch is active at
the same time that power is being delivered to the output.

It is the accepted case for something like a mag amp that relies on
'old' data to derive the correction.

Fly back and boost suffer from the right half plane zero in continuous
operation.

The delay I'm suggesting is an additional overhead present in both
continuous and discontinuous operation.

DNA

 

If the delay you're talking about is related or proportional to the duty
cycle (of the switching cycle), then why are buck converters exempt? You still
have to wait until the cycle is complete before you know what the output voltage
will be so that you can estimate what the next duty cycle should be to maintain
regulation, don't you?

Jim

 

| On Sun, 4 Apr 2004 06:29:33 +0100, "Genome" <>
posted this:
|
| >
| >|
| >| Delays are always a element in sampled systems. You can't correct
for
| >| something before you know what it is. A switch mode supply won't
give
| >you an
| >| indication of what the output voltage is until after the switch
cycle
| >is
| >| complete. In effect, it's a sampled system with all that implies.
| >|
| >| Jim
| >|
| >|
| >
| >Not true for buck and buck derived converters. The switch is active
at
| >the same time that power is being delivered to the output.
| >
| >DNA
| >
|
| If the delay you're talking about is related or proportional to the
duty
| cycle (of the switching cycle), then why are buck converters exempt?
You still
| have to wait until the cycle is complete before you know what the
output voltage
| will be so that you can estimate what the next duty cycle should be to
maintain
| regulation, don't you?
|
| Jim
|

That is the case for flyback and boost. Energy is stored in the inductor
and subsequently delivered during the switch off time. The loop is
controlling the energy being stored whilst monitoring an output to which
the energy is not being delivered. You do have to wait for the switching
cycle to complete before you get the answer.

In buck or buck derived the loop is controlling energy being stored and
delivered via the inductor whilst monitoring the output to which that
energy is being delivered. You don't have to wait for the switching
cycle to complete before you get the answer.

I'm not suggesting that there isn't some nature of sampled systems that
each converter must obey, rather that the flyback/boost has an
additional delay inherent in the system due to the way energy is
stored/delivered.

I guess that helps clarify why the delay is proportional to switch on
time rather than switch off time, it does it for me anyway.

DNA

 

I'm still unconvinced. A buck regulator switching element is usually
driven from a PWM source. If you set a particular PW based on the present
output voltage, you won't be able to set a different PW until the first one
times out. That's the delay I was pointing out.

Jim

 

| On Sun, 4 Apr 2004 20:35:20 +0100, "Genome" <>
posted this:
|
|
| >In buck or buck derived the loop is controlling energy being stored
and
| >delivered via the inductor whilst monitoring the output to which that
| >energy is being delivered. You don't have to wait for the switching
| >cycle to complete before you get the answer.
| >
| >DNA
| >
|
| I'm still unconvinced. A buck regulator switching element is usually
| driven from a PWM source. If you set a particular PW based on the
present
| output voltage, you won't be able to set a different PW until the
first one
| times out. That's the delay I was pointing out.
|
| Jim
|

I can't really argue against your reasoning for the case you state in
isolation. I can only suggest that there is a difference between buck
and flyback by virtue of the relative timing between control and
delivery of power.

The simulations require a delay for flyback if the linear model is to
agree with the switching model, and the agreement is precise.

DNA

 

The delay you state is associated with all topologies having right hand
plane zeroes such as the Boost and Flyback. That is because if there is any
change in pulse width they must store this new value for a complete Ton
cycle before it can be passed to the output while other Buck like topologies
can pass or transform the new value immediately, no storage cycle necessary.
Sound like the delay should equal: D=L/(Ro*Toff*Fs).
Maybe I am preaching to the choir.
Harry

 

|
| | >
| > | > | On Sun, 4 Apr 2004 20:35:20 +0100, "Genome" <>
| > posted this:
| > |
| > |
| > | >In buck or buck derived the loop is controlling energy being
stored
| > and
| > | >delivered via the inductor whilst monitoring the output to which
that
| > | >energy is being delivered. You don't have to wait for the
switching
| > | >cycle to complete before you get the answer.
| > | >
| > | >DNA
| > | >
| > |
| > | I'm still unconvinced. A buck regulator switching element is
usually
| > | driven from a PWM source. If you set a particular PW based on the
| > present
| > | output voltage, you won't be able to set a different PW until the
| > first one
| > | times out. That's the delay I was pointing out.
| > |
| > | Jim
| > |
| >
| > I can't really argue against your reasoning for the case you state
in
| > isolation. I can only suggest that there is a difference between
buck
| > and flyback by virtue of the relative timing between control and
| > delivery of power.
| >
| > The simulations require a delay for flyback if the linear model is
to
| > agree with the switching model, and the agreement is precise.
| >
| > DNA
| >
| >
| The delay you state is associated with all topologies having right
hand
| plane zeroes such as the Boost and Flyback. That is because if there
is any
| change in pulse width they must store this new value for a complete
Ton
| cycle before it can be passed to the output while other Buck like
topologies
| can pass or transform the new value immediately, no storage cycle
necessary.
| Sound like the delay should equal: D=L/(Ro*Toff*Fs).
| Maybe I am preaching to the choir.
| Harry
|

I think I've joined a different choir.

I'm suggesting that the delay and the right half plane zero are two
separate entities and the delay is active for both discontinuous and
continuous operation

If you saw the original post and the post to the binaries group then you
will notice that the particular converter I was dealing with was
operating in the discontinuous mode, hence... no right half plane zero.

The linear and switching models only match each other if I include a
delay of Ton in the linear model and, as suggested the agreement is
good.

With my limited maffs the right half plane zero drops out at....

frhpz = VIN/2piLpri.ILpri

Not the standard form but the standard form takes things further in an
attempt to include the duty cycle and load. I prefer the above.

Most texts come up with some such thing as 'you have to close the loop
at 1/10th of the RHPZ' which isn't really good enough. I think it's a
rule of thumb that has arisen because the delay hasn't been
included.....

A case of it's bad but, for some reason, it's worse than we expected.

DNA

 

If ... Frhpz=Vin/(2*pi*Lp*dI)
then ....Delay= Ton (simple math)
This makes sense, you must wait a complete Ton before you can go store up
the new energy requirement. Buck topologies can supply the correct energy by
just extending their Ton time. No need for added time to store. This is true
in continuous and discontinuous mode of operation. The discontinuous mode
eliminates the stability problems but the same delay should be there.
Are we saying the same thing?
Harry

 

|
| | >
| > | > |
| > | | > | >
| > | > | > | > | On Sun, 4 Apr 2004 20:35:20 +0100, "Genome"
<>
| > | > posted this:
| > | > |
| > | > |
| > | > | >In buck or buck derived the loop is controlling energy being
| > stored
| > | > and
| > | > | >delivered via the inductor whilst monitoring the output to
which
| > that
| > | > | >energy is being delivered. You don't have to wait for the
| > switching
| > | > | >cycle to complete before you get the answer.
| > | > | >
| > | > | >DNA
| > | > | >
| > | > |
| > | > | I'm still unconvinced. A buck regulator switching element is
| > usually
| > | > | driven from a PWM source. If you set a particular PW based on
the
| > | > present
| > | > | output voltage, you won't be able to set a different PW until
the
| > | > first one
| > | > | times out. That's the delay I was pointing out.
| > | > |
| > | > | Jim
| > | > |
| > | >
| > | > I can't really argue against your reasoning for the case you
state
| > in
| > | > isolation. I can only suggest that there is a difference between
| > buck
| > | > and flyback by virtue of the relative timing between control and
| > | > delivery of power.
| > | >
| > | > The simulations require a delay for flyback if the linear model
is
| > to
| > | > agree with the switching model, and the agreement is precise.
| > | >
| > | > DNA
| > | >
| > | >
| > | The delay you state is associated with all topologies having
right
| > hand
| > | plane zeroes such as the Boost and Flyback. That is because if
there
| > is any
| > | change in pulse width they must store this new value for a
complete
| > Ton
| > | cycle before it can be passed to the output while other Buck like
| > topologies
| > | can pass or transform the new value immediately, no storage cycle
| > necessary.
| > | Sound like the delay should equal: D=L/(Ro*Toff*Fs).
| > | Maybe I am preaching to the choir.
| > | Harry
| > |
| >
| > I think I've joined a different choir.
| >
| > I'm suggesting that the delay and the right half plane zero are two
| > separate entities and the delay is active for both discontinuous and
| > continuous operation
| >
| > If you saw the original post and the post to the binaries group then
you
| > will notice that the particular converter I was dealing with was
| > operating in the discontinuous mode, hence... no right half plane
zero.
| >
| > The linear and switching models only match each other if I include a
| > delay of Ton in the linear model and, as suggested the agreement is
| > good.
| >
| > With my limited maffs the right half plane zero drops out at....
| >
| > frhpz = VIN/2piLpri.ILpri
| >
| > Not the standard form but the standard form takes things further in
an
| > attempt to include the duty cycle and load. I prefer the above.
| >
| > Most texts come up with some such thing as 'you have to close the
loop
| > at 1/10th of the RHPZ' which isn't really good enough. I think it's
a
| > rule of thumb that has arisen because the delay hasn't been
| > included.....
| >
| > A case of it's bad but, for some reason, it's worse than we
expected.
| >
| > DNA
| >
| If ... Frhpz=Vin/(2*pi*Lp*dI)
| then ....Delay= Ton (simple math)
| This makes sense, you must wait a complete Ton before you can go
store up
| the new energy requirement. Buck topologies can supply the correct
energy by
| just extending their Ton time. No need for added time to store. This
is true
| in continuous and discontinuous mode of operation. The discontinuous
mode
| eliminates the stability problems but the same delay should be there.
| Are we saying the same thing?
| Harry
|

I believe we are

DNA

 

Well...er...a hysteretic buck or boost doesn't really have this problem
of waiting. As soon as the output voltage goes outside the window, the
switch will turn on or off, essentially immediately. Of course, current
still flows giving some effective delays, but there is no wait for a
next cycle. Its a variable frequency pwm, the frequency (sample time)can
go up to infinite, in principle.

Kevin Aylward

http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

| didn't Ray Ridley cover this in his PhD thesis......where he applied a
| sampled-data model to the "standard" model of a current-mode
controlled
| supply, to come up with a "more accurate" model (up to nyquist
frequency at
| any rate)
|
| A bit of talking at cross-purposes perhaps, but the buck-vs-boost
discussion
| is interesting, and of course the basis of the RHP zero is well
described.
|
| Regardless of buck or boost topology though, they share the common
behaviour
| of any sampled data system - you have to wait (up to a whole period)
for the
| system to respond to any load change when the control system isnt
"looking"
| (during Ton for boost, Toff for buck).
|
| Ive looked into the discrete-time modelling of control systems a fair
bit,
| and there are various ways of modelling this delay (Zero-Order Hold,
e^sT
| delay, BLT, augmented controllers etc) but its certainly there...
|
|
|

Subharmonic oscillation is a case of division by halves. Ray Pidley
sells network analysers and can't cope with the idea of discontinuity in
modes of operation. He probably thinks he is Einstein.

I don't think the RHPZ is well described.

The difference is that the flyback never gets to look the buck does.

Try sticking a transmission line in your linear model with the delay set
to TON. It works.

DNA

Oooooop, I didn't type that.

 

| Terry Given wrote:
| > didn't Ray Ridley cover this in his PhD thesis......where he applied
a
| > sampled-data model to the "standard" model of a current-mode
| > controlled supply, to come up with a "more accurate" model (up to
| > nyquist frequency at any rate)
| >
| > A bit of talking at cross-purposes perhaps, but the buck-vs-boost
| > discussion is interesting, and of course the basis of the RHP zero
is
| > well described.
| >
| > Regardless of buck or boost topology though,
|
| Oh....
|
| >they share the common
| > behaviour of any sampled data system - you have to wait (up to a
| > whole period) for the system to respond to any load change when the
| > control system isnt "looking" (during Ton for boost, Toff for buck).
|
| Well...er...a hysteretic buck or boost doesn't really have this
problem
| of waiting. As soon as the output voltage goes outside the window, the
| switch will turn on or off, essentially immediately. Of course,
current
| still flows giving some effective delays, but there is no wait for a
| next cycle. Its a variable frequency pwm, the frequency (sample
time)can
| go up to infinite, in principle.
|
| Kevin Aylward
|
| http://www.anasoft.co.uk
| SuperSpice, a very affordable Mixed-Mode
| Windows Simulator with Schematic Capture,
| Waveform Display, FFT's and Filter Design.
|
| "quotes with no meaning, are meaningless" - Kevin Aylward.
|
|

But..... hysteretic controllers are DIRT.

If you turn your head to critical mode conduction then you can analyse
it a bit. Nice things do happen.

And.......

The same arguments of buck versus flyback/boost still apply.

DNA

 

Why would they be dirt in a buck configuration - well anyway if we have
circuit to eliminate saturation of the inductor?

Cheers

Klaus

 

| | >
message
| > | > | Terry Given wrote:
| > | > didn't Ray Ridley cover this in his PhD thesis......where he
applied
| > a
| > | > sampled-data model to the "standard" model of a current-mode
| > | > controlled supply, to come up with a "more accurate" model (up
to
| > | > nyquist frequency at any rate)
| > | >
| > | > A bit of talking at cross-purposes perhaps, but the
buck-vs-boost
| > | > discussion is interesting, and of course the basis of the RHP
zero
| > is
| > | > well described.
| > | >
| > | > Regardless of buck or boost topology though,
| > |
| > | Oh....
| > |
| > | >they share the common
| > | > behaviour of any sampled data system - you have to wait (up to a
| > | > whole period) for the system to respond to any load change when
the
| > | > control system isnt "looking" (during Ton for boost, Toff for
buck).
| > |
| > | Well...er...a hysteretic buck or boost doesn't really have this
| > problem
| > | of waiting. As soon as the output voltage goes outside the window,
the
| > | switch will turn on or off, essentially immediately. Of course,
| > current
| > | still flows giving some effective delays, but there is no wait for
a
| > | next cycle. Its a variable frequency pwm, the frequency (sample
| > time)can
| > | go up to infinite, in principle.
| > |
| > | Kevin Aylward
| > |
| > | http://www.anasoft.co.uk
| > | SuperSpice, a very affordable Mixed-Mode
| > | Windows Simulator with Schematic Capture,
| > | Waveform Display, FFT's and Filter Design.
| > |
| > | "quotes with no meaning, are meaningless" - Kevin Aylward.
| > |
| > |
| >
| > But..... hysteretic controllers are DIRT.
| >
| > If you turn your head to critical mode conduction then you can
analyse
| > it a bit. Nice things do happen.
| >
| > And.......
| >
| > The same arguments of buck versus flyback/boost still apply.
| >
| > DNA
| >
|
| Why would they be dirt in a buck configuration - well anyway if we
have
| circuit to eliminate saturation of the inductor?
|
| Cheers
|
| Klaus
|
|

You are quite right.

DNA

 

No idea what DIRT means.


Kevin Aylward

http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

didn't Ray Ridley cover this in his PhD thesis......where he applied a
sampled-data model to the "standard" model of a current-mode controlled
supply, to come up with a "more accurate" model (up to nyquist frequency at
any rate)

A bit of talking at cross-purposes perhaps, but the buck-vs-boost discussion
is interesting, and of course the basis of the RHP zero is well described.

Regardless of buck or boost topology though, they share the common behaviour
of any sampled data system - you have to wait (up to a whole period) for the
system to respond to any load change when the control system isnt "looking"
(during Ton for boost, Toff for buck).

Ive looked into the discrete-time modelling of control systems a fair bit,
and there are various ways of modelling this delay (Zero-Order Hold, e^sT
delay, BLT, augmented controllers etc) but its certainly there...

 

most arguments against hysteretic control are related to the lack of control
over switching frequency (a real problem with IGBTs), and problems
associated with filtering a "non-constant" switching frequency, but I bet
most of the "problems" are due to people having difficulty making them work
properly, i.e. the usual suspects.

There are plenty of ways of gaining some/full control over switching
frequency though, and the filtering issue is unlikely to be a showstopper,
but they are still uncommon. They will all tend to "hiccup" when lightly
loaded, as there will always be a minimum pulse width for the switching
device: if the resultant minimum pulse energy > load requirement, output
voltage will rise. Again, this is unlikely to cause any real problems.

If you look at something like the roman black smps (cute), you'll see
another problem - an output short-circuit will destroy the smps. The
aforementioned hysteretic controller needs to be a hysteretic current
controller to prevent this (same reason of course that current control is
used almost exclusively in PWM - it deals with fault conditions, rather than
blowing up (at least it should....;-))

and by the time you run into minimum on and off times, your hysteretic
current controller starts to look just like a sampled data system, which of
course it always was, just an asynchronous, event-triggered (which is what
"gets rid of" the delay discussed in this thread) sampled data system. What
it "looks" like from a control loop perspective is a very high gain, so the
output current "exactly" follows the setpoint current; the hysteretic
current controller then has a finite "gain" - the ratio of control volts to
output amps. If you look hard enough, you will see the effects of min Ton
and Toff though.....probably looks like a pole at half the resultant quite
high (but not infinite) switching frequency (it is likely that the
Fcrossover = 1/10 Fsw comes from being 1/5 of the nyquist frequency = Fsw/2,
so a pole at Fnyq only contributes about 11 degrees of phase shift, which
can be conveniently ignored)


The overall system dynamics therefore end up being governed by the voltage
control error amp, the current controller gain and the output capacitance.
In practice the current controller and the output cap limit the available
dynamic performance - when I is limited, dV/dt = I/C is likewise limited;
when the voltage across the inductor is limited, dI/dt = V/L is also
limited - well before any of the unavoidable sampled-data effects come into
play (in other words, they work). This is of course a fundamental result,
and is why so many modern buck smps switch very fast, and use extremely low
output inductors

The corollary of course is that one really needs to know the sort of dynamic
performance that is required from the power supply to be designed (specified
as step load changes, isnt that right Kevin...*lol*) before selecting an
appropriate solution; alas that is usually not the case - hell, your doing
pretty well if you know the desired output voltage, let alone the
current.......