Mike,
Thanks for explanation. I've used a delay line to provide accurate phase shifts in a
bridge simulation but it always simulates slowly. Now I'll try the bv model and see if
there is a difference. For this case a simple RC delay wouldn't work well, as you
note, since it doesn't preserve the waveform.
George
Mike Engelhardt wrote:
George,
They use slightly different timestep control algorithms, so
it should be possible to contrive simulations that will
demonstrate each as faster. Neither is ever used in the
SMPS macro models because these IC's don't contain high
fidelity analog delay lines. Analog delays in LTspice's
SMPS macro models are usually RC time constants. They
better mimic the delay of something like a comparator
because they will switch state faster given more over-
voltage and switch slower if the input slowly approaches
the threshold. Real comparators act somewhere between
integrators and discrimators. Anyway, RC time constants
in this case are not only more accurate, but simulate much
faster than any delay device. When looking for a delay,
one should ask if they really mean a delay that preserves
the whole analog waveform. A critter like that is much
less common then some gate that gives some delay.
--Mike
snip
