LS373 latches and offset output enable...

[Jules]

Hi,

Any ideas how to achieve the following:

Using an LS374 octal latch, under control of a *single* control line, I'd
like to be able to both latch data and switch the outputs from high
impedance to low impedance, without risk of any 'junk' dat appearing on
the outputs of the latch whilst /OE is low.

In other words, I need to set enable to low so that the data present
on the input at that time is latched, wait a little, then enable the
outputs by setting /OE to low.

At a future time I need to disable the outputs by setting /OE to high,
*then* set the enable input to high so that outputs of the latch follow
the inputs again.

In this way the outputs of the LS373 are always either latched data or
high impedance - there's never any fluttering of outputs.

Problem is my need to do this with a single external enable line - as on
the external enable going high I want to change the LS373's enable
line before the /OE line, but on the external enable going low again I
want to change the /OE line before the chip's enable line.

I assume if I want to introduce a delay I can just couple a pair of
inverters together, but that doesn't fix the need for the delay to be on a
different pin of the LS373 depending on the state of the external enable
line.

thoughts?

cheers

Jules

 

[Tony Williams]

[snip]

Problem is my need to do this with a single external enable line
- as on the external enable going high I want to change the
LS373's enable line before the /OE line, but on the external
enable going low again I want to change the /OE line before the
chip's enable line.

I assume if I want to introduce a delay I can just couple a pair
of inverters together, but that doesn't fix the need for the
delay to be on a different pin of the LS373 depending on the
state of the external enable line.

You simply want LATCH to be instant for an incoming
-ve edge and delayed for a +ve edge whereas /OE
should have the opposite edge responses.

Selective delays (+ve or -ve edge) can be done with
any two-input logic gate.

___
In --+----------------| |
| R |NOR|o----Out
+--/\/\--+-------|___|
|
===C
|
--+--0v

That will have a delayed response to an Input -ve
edge and an instant response to a +ve edge.

Two such circuits and a few inverters should do what
you want. Maybe do it with one quad 2-input NOR.

If you don't like the RC network it can be replaced
by a string of non-inverting gates.