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Low Speed Clock Recovery Chip

Discussion in 'Electronic Design' started by stevieboy01, Apr 18, 2005.

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  1. stevieboy01

    stevieboy01 Guest

    Does anyone have any ideas about available chips suitable for clock
    recovery and data retiming on low speed (40kbps)? All the ones I can
    find are for Gbps and are not what I am looking for.

    The data currently is 4 level ASK with fairly good noise properties.

    Any ideas would be much appreciated, I dont really have any
    thoughts......
     
  2. Tim Shoppa

    Tim Shoppa Guest

    clock recovery and data retiming on low speed (40kbps)?

    A CD4046/74HC4046 type PLL may do fine, as would a digital PLL clocked
    at many times 40kHz. How many times depends on maximal time between
    transitions.
    Of some importance is how long a valid data stream can go without any
    transitions - this obviously depends on encoding, and it directly
    drives the loop filter optimization. If you're guaranteed a transition
    at every boundary, simple differentiation and an edge-sensitive phase
    comparator may do the trick. Beware, though, just because the signal
    itself may look clean, the differentiated signal may not be!

    Tim.
     
  3. stevieboy01

    stevieboy01 Guest

    Many thanks Tim, will look into this solution.

    All the best.
     
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