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Low power quartz oscillator problem (two frequencies)

Discussion in 'Electronic Design' started by Miguel Gimenez, Jul 21, 2004.

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  1. I'm using a TI MSP430 microcontroller. It has a low power oscillator
    suitable for 32768 Hz quartzs that is internally multiplied for CPU usage.

    For a frecuency meter application, I'm feeding the 32768 signal to a timer
    and counting transitions of a signal between two timer IRQs. The readings
    were affected by a "jitter" that, after inspection, was caused by IRQs
    firing with an uncertainty of 375 ns over 1 ms.

    Looking with the oscilloscope the quartz signal, there are two frequencies:
    the nominal (32768) and other about 2500 Hz above and 10 dB lower. Also
    appears the difference between the two.

    Other brands of quartz show the same behaviour. The quartz is guarded and
    the traces are short (about 3 mm).

    If I change the 32768 quartz by a 4 MHz one, the jitter dissapears (down to
    3 ns) and the readings are OK, but the CPU draws a lot more power and the
    lythium battery life is too short.

    Please, tell me how can I eliminate this second frequency. I have read about
    "spurious modes" in quartzs, but I don't know if this is the case, and it's
    strange that various brands show the same behaviour.


    Best regards
    Miguel Giménez
     
  2. ddwyer

    ddwyer Guest

    The extra frequency 2500Hz above could be either du to a quartz spurious
    or something in the internal structure of the processor.
    If the problem lies with the crystal:
    Unwanted spurious are designed to be higher resistance than the wanted.
    An oscillator maintaining circuit that activates an unwanted spurious
    has gain too high.
    If the oscillator circuit employs capacitors to ground at the two ends
    of the crystal then the gain can be reduced by increasing these
    capacitors say from 15 pf to 30 or 50pF by experiment. This will move
    the frequency down by ppm but this can be raised by introducing an
    additional series capacitor with the crystal.
    Note that as crystals get smaller their potential to be over driven
    increases so that a series resistor will decrease the current through
    the crystal.
     
  3. J M Noeding

    J M Noeding Guest

    it is presented some arguments which are not really important,
    it is no difficulties involved making a "4MHz" cmos oscillator with
    divider, using a '4060 is a suggestion. It is many readily available
    xtals in the region of 2-14MHz, so I don't really see the reason for
    choosing 4MHz

    jm
     
  4. Phil Hobbs

    Phil Hobbs Guest

    Crystal oscillators run at a frequency at which the round-trip phase is
    0 degrees, but there can be more than one such place, since the crystal
    is not a simple inductor. Your crystal may be wanting to run too close
    to its series resonance for the crystal tank circuit to have a single
    well-defined resonance. (High-overtone crystals often show this
    behaviour since they look capacitive at all frequencies, and the same
    capacitive reactance will occur on both sides of resonance.) Something
    to try would be putting a lowish-value capacitor (say 100 pF or 470 pF)
    in series with the crystal, to shift the resonance to a frequency where
    the crystal itself is more inductive.

    Cheers,

    Phil Hobbs
     
  5. Joerg

    Joerg Guest

    Hi Miguel,

    It could also be something caused by another part of the circuitry. Is
    the power supply properly bypassed? Can you see those 2500Hz anywhere
    else, on any other pin?

    Regards, Joerg
     
  6. Tim Shoppa

    Tim Shoppa Guest

    Keep in mind that the 32768 kHz oscillator is swinging about 3V in
    1/32768th of a second. That's a slew rate of only 0.2V or so per microsecond.
    In terms of digital logic thresholds, that's a glacially slow rate, and even
    though there's a Schmitt trigger to clean it up you will be quite sensitive
    to other noise sources and modulations on your Vcc which will vary the
    Schmitt trigger threshold.
    Keep in mind that the 4MHz crystal will be slewing around 20V/microsecond...
    a much better clip.
    I don't think this is so much a spurious mode of the quartz... my gut feeling
    is that variations in Vcc (possibly related to an output load toggled by the
    processor?) changing the Schmitt trigger thresholds at the oscillator
    input.

    I believe that I've seen app notes (Dallas Semi?) about putting guard
    traces around the oscillator pins and components to reduce some of the noise
    effects, but in the case of phase modulation through Vcc variations this
    won't help. I think it does help with the inherent high input impedances
    associated with low power oscillators.

    Can you lengthen the counting interval?

    Tim.
     
  7. ddwyer

    ddwyer Guest

    32kHz osc charges capacitors less often so draws less power.
     
  8. I had the usual decoupling capacitors near the Vcc pins, then added a 15 ohm
    series resistance. I have tested the circuit with the lythium battery and an
    external power supply, with same results. I'll check the ground plane
    tracing.
    It's recommended by Texas. I have no noisy lines near the quartz traces, and
    they are very short. The only drawback can be that the quartz is on the back
    of the uP connected by two vias.
    The circuit must track the frequency variation caused by a moving part, the
    counting interval is hardly modifiable.
    Best regards
    Miguel Giménez
     
  9. I have a 15 Ohm series resistor and a 100nF capacitor just in the uP power
    pins. I have tested higher resistors (upto 270 Ohm) and capacitors (from 1uF
    to 1000uF). The supply is a 3V lythium battery, in parallel with a 68uF
    tantalum capacitor and a 100nF ceramic capacitor, all SMD.

    The uP's only task is
    - sleep waiting for IRQ (only oscillator runs)
    - read and store counter data
    - loop

    repeating each milisecond. No other pins change, except the input for the
    measured signal that is about 8 MHz.

    I'll check the ground plane and the guard ring.

    Best regards
    Miguel Giménez
     
  10. Following your indications I have tested capacitors from 22 pF to 15 nF.
    With 1 nF the jitter reduces to about 1/3 , but it's still there. The Pierce
    capacitors are inside the uP, so I only can test in series with the quartz
    itself, no with the XOut line as seen in some documents.

    I'll check the PCB traces, the guard ring and the ground plane.

    Thanks
    Miguel Giménez
     
  11. Tim Shoppa

    Tim Shoppa Guest

    Decoupling is good, but if there are internal impedances going to the
    oscillator then the phase modulation that I am postulating can't be
    gotten rid of by all the external decoupling in the world. The
    15 ohm series resistance you added may make things worse if
    the noise is coming from the MSP430's innards.

    Is there any chance you have enough board real estate to make an
    external 32.768kHz oscillator? That you could probably decouple
    well enough. All you really need is an inverter for the oscillator,
    another inverter for an output buffer (kindof optional), an R and two
    C's.

    Most applications for 32.768kHz oscillators will not be sensitive
    to the phase noise/jitter that you are seeing. That's good for
    those applications, but not good for yours, because most microcontrollers
    emphasize low power consumption and reliable starting over your needs.
    What is your counting interval, what's the frequency, and what are
    the constraints? If 300ns of jitter in the 32.768kHz clock is important,
    I'm guessing that you are counting in the 10 MHz region and that the
    resulting jitter is in the last digit, if the interval is around 1 sec.

    Tim.
     
  12. Tim Shoppa

    Tim Shoppa Guest

    Ah, the "repeating each millisecond" is a good clue, especially if
    you are observing a 2 kHz phase noise phenomenon. Think about it: the
    MSP430's power consumption spikes by a factor of 100 each time
    it wakes up. Can you modify your code so that it never falls
    asleep (idle loops instead, maybe?)

    Tim.
     
  13. Tim Wescott

    Tim Wescott Guest

    If you can't access the capacitors (very bummer) you should seriously
    consider trying different brands of crystals. Spurious resonances in
    crystals is something that is more or less under the manufacturer's
    control, if they care.
     
  14. If I do that the problem gets worse, but for a different reason: the IRQ
    isn't serviced until the end of the current instruction, so I'm adding an
    uncertainty of 0 to 3 cycles, 250 ns each.
    I have little board available and the two sides are populated. I would need
    also a disable pin, as the board is never disconnected: the uC goes to "deep
    sleep" mode instead of powering off. Maybe a good solution for the 2.0
    version.
    I'm counting during about a millisecond (4,096 / 4,000,000), the frequency
    is about 8 MHz, and I need the second derivative in order to calculate the
    acceleration of the probe. The jitter produces a random (actually almost
    cyclical with a 5 sample period) error from 0 to 10 units over the 0 to 60
    scale (unusable). With the 4 MHz (or 2 MHz) quartz, I have an error less
    than 0.5 units caused almost entirely by mechanical issues. The scope shows
    a jitter of about 2 ns. I'm thinking about connecting a popular 1.8432 MHz
    quartz for the first batch.
    Thank you
    Miguel Giménez
     
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