Low jitter transmission of LVDS signals

[Spehro Pefhany]

I want to transmit a few LVDS clock signals (<= 10MHz) over a meter or
so of wire each.

What's the best kind of wire to use to minimize added jitter? Just
need a single shielded twisted pair and (preferably) a wire for a
ground reference.

A low smoke/zero halogen type would be very good.


Best regards,
Spehro Pefhany

 

[Robert Macy]

I want to transmit a few LVDS clock signals (<= 10MHz) over a meter or
so of wire each.

What's the best kind of wire to use to minimize added jitter? Just
need a single shielded twisted pair and (preferably) a wire for a
ground reference.

A low smoke/zero halogen type would be very good.

Best regards,
Spehro Pefhany

don't know about your low smoke requirement, but look at
Belden 1800F
I believe it's Zc = 110 ohms

 

[Spehro Pefhany]

How low do you want the added jitter to be?

Not completely sure at the moment, but I think it has to be < 10ps for
the added noise to be < 1 lsb. The source oscillator is claimed to
have < 1ps jitter, so it should be negligible, but it's going through
some logic too. It's a delta-sigma clock.

A 100 ohm shielded pair with a braid or drain, grounded on both ends, should be
pretty good. Use a fast driver and an LVDS receiver with a symmetric threshold,
not one with a big deliberate offset. I'm partial to FIN1101, a real screamer.

https://dl.dropbox.com/u/53724080/Parts/Logic/FIN1101_DC_Offset_Graph_3.3Vcc.pdf

Nice part, any reason not to standardize on it, other than a slight
cost premium? No problems with ESD?

I'm using ye olde SN65LVDS parts which I think are symmetric.

 

[[email protected]]

I want to transmit a few LVDS clock signals (<= 10MHz) over a meter or

so of wire each.



What's the best kind of wire to use to minimize added jitter? Just

need a single shielded twisted pair and (preferably) a wire for a

ground reference.



A low smoke/zero halogen type would be very good.

Have you checked National's LVDS Owner's Manual? Total jitter will depend on the length of cable too. Their measurements are way out of line with your objective.
http://www.ti.com/lit/ml/snla187/snla187.pdf

 

[[email protected]]

Cable attenuation will cause "deterministic jitter" when data patterns

are being transmitted. A continuous clock is less sensitive to

attenuation because it gets only "random jitter."



There's also the distinction between "jitter" and "wander", the

concept being that you have to pick some time span over which to

measure jitter. Wander includes the slow stuff, like thermal effects

on prop delay. The telecom people usually use 0.1 seconds as the

cutover point.





--



John Larkin Highland Technology, Inc



jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com



Precision electronic instrumentation

Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

VME thermocouple, LVDT, synchro acquisition and simulation

True, but if he runs it any distance, attenuation causes his transition times to suffer putting him back to a humdrum 20-50ps RMS jitter just due to the comparator at the receiving end, and these signals are smallish.

 

[Bill Sloman]

10 ps RMS added jitter should be easy, 1 ps feasible. Make sure all the power
supplies are quiet!

Logic? FPGAs are nasty for jitter. CMOS is mediocre. ECL, like EclipsLite, is
great.

ECL is current-steering logic, and ECL power rails have much less
"grass" than rails feeding CMOS and other voltage-switching logic.
Noise on the power rails feeds into the comparator that is detecting
the edges (Power Supply Rejection Ratios - PSRRs - are lousy at high
frequencies) This shifts the point where the comparator thinks that
the in-phase and anti-phase inputs have crossed over and thus
introduces jitter.

From an analog design point of view, jitter is the voltage noise on
the cross-over point projected onto the edge speed of the two signals
being compared. The less dispersive your cable, the better the edge
speed at the receiver end and the lower the jitter.

 

[brent]

On Tue, 02 Apr 2013 08:28:15 -0700, John Larkin

Not completely sure at the moment, but I think it has to be < 10ps for
the added noise to be < 1 lsb. The source oscillator is claimed to
have < 1ps jitter, so it should be negligible, but it's going through
some logic too. It's a delta-sigma clock.

[snip]

I'm sure happy to hear that Larkin likes my chip work...  I did that
one in April 2001.

                                        ...Jim Thompson
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I love to cook with wine.     Sometimes I even put it in the food.

Wow, you could not have scripted that better if you had tried.

 

[brent]

There's little doubt that, by now, we've made a lot more money off
FIN1101s than he has.

That is a great comeback

 

[[email protected]]

At one meter, a couple ps RMS should be easy. We trigger sampling

scopes over a meter or two of coax and get down there, ground loops

and all. LVDS over a diff pair should be better.





--



John Larkin Highland Technology, Inc



jlarkin at highlandtechnology dot com

http://www.highlandtechnology.com



Precision electronic instrumentation

Picosecond-resolution Digital Delay and Pulse generators

Custom laser drivers and controllers

Photonics and fiberoptic TTL data links

VME thermocouple, LVDT, synchro acquisition and simulation

Okay, 1 m I can believe, missed that part in the OP.

 

[brent]

On Tue, 02 Apr 2013 13:20:47 -0400, "Michael A. Terrell"

Jim Thompson wrote:
28:15 -0700, John Larkin
How low do you want the added jitter to be?
Not completely sure at the moment, but I think it has to be < 10ps for
the added noise to be < 1 lsb. The source oscillator is claimed to
have < 1ps jitter, so it should be negligible, but it's going through
some logic too. It's a delta-sigma clock.
A 100 ohm shielded pair with a braid or drain, grounded on both ends, should be
pretty good. Use a fast driver and an LVDS receiver with a symmetric threshold,
not one with a big deliberate offset. I'm partial to FIN1101, a real screamer.
[snip]
I'm sure happy to hear that Larkin likes my chip work...  I did that
one in April 2001.
  Another year and it'll be a teenager.

Like me, I recently turned 18-1/4 >:-}

   Sure, but you were always slow. ;-)

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My knee jerk reaction is to support a balance budget amendment,
however, I believe that if it were implemented the budget would get
balanced by never cutting spending (actually increasing it) and
forever raising taxes because it is "constitutionally " required. It
is better for the government to be insolvent.

 

[[email protected]]

On Tue, 02 Apr 2013 11:56:58 -0400, Spehro Pefhany

On Tue, 02 Apr 2013 08:28:15 -0700, John Larkin

How low do you want the added jitter to be?

Not completely sure at the moment, but I think it has to be < 10ps for
the added noise to be < 1 lsb. The source oscillator is claimed to
have < 1ps jitter, so it should be negligible, but it's going through
some logic too. It's a delta-sigma clock.

A 100 ohm shielded pair with a braid or drain, grounded on both ends, should be
pretty good. Use a fast driver and an LVDS receiver with a symmetric threshold,
not one with a big deliberate offset. I'm partial to FIN1101, a real screamer.
[snip]

I'm sure happy to hear that Larkin likes my chip work... I did that
one in April 2001.

Another year and it'll be a teenager.

Like me, I recently turned 18-1/4 >:-}

So you were born on Feb 29th, 1940 ?

 

[josephkk]

Not completely sure at the moment, but I think it has to be < 10ps for
the added noise to be < 1 lsb. The source oscillator is claimed to
have < 1ps jitter, so it should be negligible, but it's going through
some logic too. It's a delta-sigma clock.


Nice part, any reason not to standardize on it, other than a slight
cost premium? No problems with ESD?

I'm using ye olde SN65LVDS parts which I think are symmetric.

For your cable requirements i expect that TIA 568 certified Cat6 cable
can do the job.

?-)

 

[Spehro Pefhany]

For your cable requirements i expect that TIA 568 certified Cat6 cable
can do the job.

?-)

A little fat and physically inflexible, but that would work.


Best regards,
Spehro Pefhany