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I'm building a digital clock circuit ...
Any suggestions would be much appreciated.
Any old fool can tap into that transformer to pulse a Schmitt trigger or
comparator or what have you, but tapping into the timing in such a way
that the resulting reference clock is not cumulatively "pulled" by the
DC loading of the circuit or mains variation is an entirely different
story. What is the periodicity of the mechanicals, and what is the logic
loading and its long term cycling profile? What kind of timing accuracy
are you looking for over a 24 hour period? The answer to your problem
may be much deeper than you expect.
If the schmitt is squaring up 60 Hz cycles, how can DC offsets or
"mains variations" affect clock accuracy? If you count each line cycle
exactly once (not zero times, and not twice) where's the error?
The 60 Hz line is sort of the definition of clock time.
You are trapped into thinking about steady state. It is the transition
between steady states that causes the error to accumulate over the long
term. The '339 circuit pulls nonlinearly with line amplitude. Therefore
it will accumulate error.
OK, if 5,184,000 sine cycles go into the comparator every day, and
5,184,000 square cycles come out every day, where does the error
accumulate?
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I think the idea was that line glitches could give false triggers,
and if the comparator doesn't have hysteresis, it could oscillate during
the relatively slow transition at 50 Hz. I did this with an LM324 once,
and didn't bother with hysteresis or anything, but it was only used to
start an 8.333 ms timing loop, so any glitches (if there actually
_were_ any - I can't verify or refute that) were locked out in software.
I wonder how long the OP is going to keep this thread going before he
actually tries any of these suggestions?
Thanks,
Rich