K
krw
- Jan 1, 1970
- 0
I doubt that the national power grid will be, at any instant, much
more than a second ahead or behind, and longterm it's perfect.
Ignoring failures (which my "PLL" scheme attempts to compensate
for).
I doubt that the national power grid will be, at any instant, much
more than a second ahead or behind, and longterm it's perfect.
Exactly one square output cycle per sine input cycle, forever, sounds
fairly predictable to me.
Some day I'll explain ESD diodes to you, if you ask real nice.
Exactly one square output cycle per sine input cycle, forever, sounds
fairly predictable to me.
Some day I'll explain ESD diodes to you, if you ask real nice.
John
...and why you *really* don't want to use them as part of your
circuit, I presume.
OK, why not? I's been a couple of decades since people figured out
CMOS latchup and took suitable precautions. Modern HC parts are spec'd
to handle numbers like 50 mA without problems.
John
The "suitable precautions" only prevent frying. They don't prevent
copious amounts of substrate current flow... substantially more than
you inserted, due to PNP action.
The "diodes" (they're actually isolation tubs that, with the adjacent
diffusions, can act as bipolar transistors) are only rated for
transient ESD events, NOT for clamping slow signals.
But go ahead and use them as clamps... I certainly don't care if your
circuits up and fry for "magical" reasons.
I NEVER rely on ESD diodes for clamping... VERY BAD engineering
practice.
...Jim Thompson
The only "bad engineering practice" is doing something that doesn't
work. But usually BEP means "something I don't like."
Suppose I set up an HC14 and provide for measuring Icc. Now I force a
range of + and - currents into one input. Things that might happen
are...
1. Some parasitic transistor is turned on and Icc increases.
2. Some parasitic SCR turns on and the whole chip latches.
3. Some other phenom that I can't predict.
4. One of the above, plus the output level gets wrong.
5. None of the above, the diodes act like diodes.
So which will happen? If you'll make predictions, I'll go into the lab
and try it.
John
The only "bad engineering practice" is doing something that doesn't
work. But usually BEP means "something I don't like."
Suppose I set up an HC14 and provide for measuring Icc. Now I force a
range of + and - currents into one input. Things that might happen
are...
1. Some parasitic transistor is turned on and Icc increases.
2. Some parasitic SCR turns on and the whole chip latches.
3. Some other phenom that I can't predict.
4. One of the above, plus the output level gets wrong.
5. None of the above, the diodes act like diodes.
So which will happen? If you'll make predictions, I'll go into the lab
and try it.
John
Jim said:But go ahead and use them as clamps... I certainly don't care if your
circuits up and fry for "magical" reasons.
I NEVER rely on ESD diodes for clamping... VERY BAD engineering
practice.
I used them (on a once-off) as power supply rectifier even
74HCsomething sync amplifier to use in-line with a monitor that wanted
TTL sync while the computer output <1v. The monitor input carries no
voltage, thus I had to use external power. I thought.
When I disconnected the power the device kept working. I guess the
monitor presented a pull-up when activity was sensed and this powered
the device through the protection diode.
Thomas
I used them (on a once-off) as power supply rectifier even
74HCsomething sync amplifier to use in-line with a monitor that wanted
TTL sync while the computer output <1v. The monitor input carries no
voltage, thus I had to use external power. I thought.
When I disconnected the power the device kept working. I guess the
monitor presented a pull-up when activity was sensed and this powered
the device through the protection diode.
Thomas
The "suitable precautions" only prevent frying. They don't prevent
copious amounts of substrate current flow... substantially more than
you inserted, due to PNP action.
The "diodes" (they're actually isolation tubs that, with the adjacent
diffusions, can act as bipolar transistors) are only rated for
transient ESD events, NOT for clamping slow signals.
But go ahead and use them as clamps... I certainly don't care if your
circuits up and fry for "magical" reasons.
I NEVER rely on ESD diodes for clamping... VERY BAD engineering
practice.
Keith said:It's still digital. ;-)
Joerg said:Hello Keith,
You just hook up a piezo and count the clicks ))
But seriously, if his clock has a uC it might already contain Schmitt
inputs. Or at least a comparator that can be "schmitted". All it then
takes is an RC to get rid of the bulk of the noise issues.
Keith said:Both. But when people ask these sorts of questions I'm primarily
worried about them, rather than some magic smoke.
You can do that because it is isolated (sometimes it's unclear
exactly what someone is intending). I'd still vote for the
suspenders to go along with the belt. Optical isolators are cheap
and may not add anything to the BOM.
Robert said:On Tue, 23 May 2006 14:44:51 -0400,
That's nuts. If your circuit is directly connected to the transformer's
secondary, an optical isolator (OI) gains nothing in case of transformer
isolation failure.
krw said:NO, I'm saying that an isolation must be used (think series). It
wasn't clear that he was tapping off an isolated secondary.
Christopher said:The transformer has a tapped winding. The first part of the winding is
connected to a linear power supply which provides the 5 V for the TTL.
The second part provides the 50 Hz signal which is to be counted.
I'm
proposing to connect one end of the second part of the winding
to the
Schmitt trigger input,
and the other end to the lower TTL power rail.
Current could flow from the first part of the winding, through the
linear power supply, through the lower power rail, and back into the
second part of the winding.
I think the circuit might still work if I
just connected one end of the second part of the transformer winding to
the Schmitt trigger input,
and left the other end unconnected,
but this
doesn't seem quite right as one end is left floating.
Taking the signal
from one end of the winding only doesn't seem quite right.
John said:but insert a
100K resistor in series, then a 22 nF cap to logic ground. That will
both limit schmitt input current
Joerg said:Hello John,
That's pretty much how I have seen it done. Also, it is not necessary to
provide a "personal winding" to the Schmitt input (although it might
make the Schmitt feel really important, if Schmitts have feelings...).
Most of the time both sides of the transformer are used for power, for a
more efficient rectification. Then the 100K just goes to one winding
before the diode.