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Looking for Help with ADF4002 Based Offset-PLL

Discussion in 'Radio and Wireless' started by buck8pe, Aug 10, 2020.

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  1. buck8pe


    Aug 10, 2020
    Hi Guys,

    Let me start by saying I'm quite a bit out of my depth here, so this is an appeal for good books more than anything else. That said, I'm trying to build a frequency synthesizer that tunes from 30.5MHz to 32MHz with coarse and fine tuning capability (it's going to be used as an LO in a transceiver build). I opted to use the ADF4002 as the PLL IC with fine tuning provided by a AD9851 DDS module in an offset-PLL configuration shown below.

    I used the Analog Devices ADISim tool to calculate the low-pass filter (LPF) and I initially opted for a 4-pole active design. This worked fine for the coarse tuning, which is provided by changing the N count in the ADF4002 with no mixer or BPF included in the loop. However, as soon as I wired up the mixer and BPF, the loop wouldn't lock and I suppose thinking about it now, that's not a surprise.

    The BPF is a modified 3rd order Cheby and the mixer is a NE612. I posted a question on SE ( https://electronics.stackexchange.c...ency-for-a-mixed-signal-frequency-synthesizer ) at the time, which will provide more detail.

    I've since opted for a much simpler 2-pole filter:

    I'm about to try this simpler filter but I'm not entirely optimistic it will work. I've been doing some research on offset-PLL topologies and I'm struggling to find the answers I'm looking for. So, here are my (simple) questions:

    If I want to model this analytically, should I be concerned about the effect of the bandpass filter and mixer (the problem is the ADISim tool has no idea they exist in the loop)?

    Any recommendations for books with a strong analytical treatment of offset-PLL architectures?

    Any practical recommendations on how to measure the effect of the mixer and filter in-circuit so that I can make some adjustments to a standard loop transfer function?
  2. buck8pe


    Aug 10, 2020
    OK, well my research is progressing and I've managed to source a copy of Ulrich Rohde's Digital PLL Frequency Synthesizers which seems well regarded. He has more to say on the subject of mixer conversion within PLL loops than other references I've read and in particular he comments on the effect of the BPF.

    On pg 44/45 he introduces a new box into the PLL loop to account for the phase shift contribution of the filter. In this case, it's a LP equivalent of a BPF where you're expected to plug in the delay.

    In the end, he concludes that the phase margin will be greater than 45 degrees recommended for higher-order loops. So, I have two ways to proceed:

    1) I can try to characterize my BPF to determine the phase delay and factor that into the loop. I'm guessing this will lead me down the path of a formal linear transfer function of my existing (3rd order) loop, including the BPF. This is probably a worthwhile exercise anyway but it's unfamiliar territory for me! I suppose I could use lt-spice or my nano-vna to try figure out the phase details and I can use the equations supplied by Rohde for the basic 3rd order loop. Any advice here?

    2) A much simpler way might be to take Rohde's advice and understand that in the end, the phase margin will increase. So, you could just bump up the phase margin parameter in ADISim and keep replacing them caps until you get a stable loop. I'd feel dirtier using this approach, but I'd probably be done a lot faster.

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