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Logic set up times and hold times

Discussion in 'General Electronics Discussion' started by willwatts, Nov 15, 2014.

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  1. willwatts

    willwatts

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    When dose a technician measure the logic setup times and hold times?
     
  2. hevans1944

    hevans1944 Hop - AC8NS

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    Never. You get this information from the device datasheet and then make sure your logic circuit complies with the specifications.
     
  3. willwatts

    willwatts

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    What about when a test technician using a logic analyzer to test and check the setup times and hold times? i thought you test the setup times and hold times when you see a flip flop or register on a schematic

    Would I use ALT mode or CHOP mode when testing the setup times and hold times?
     
  4. hevans1944

    hevans1944 Hop - AC8NS

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    If you are troubleshooting a logic circuit that doesn't work, or has intermittent problems, you measure the actual set-up and hold times with an oscilloscope to verify that they meet the device specifications. You trigger the scope on the clock edge that causes the flip-flop to change states, or the register to load or shift, and observe the data setup time on a single channel. No need for alternating or chopped display. IF the data is not stable at the clock edge, then you have failed the setup or hold time required for the device.
     
  5. willwatts

    willwatts

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    You trigger the scope on the clock edge that causes the flip-flop to change states, or the register to load or shift,

    So I use the External trigger input on the Oscope to inject the clock signal?
    I use ch1 and probe the data signal?

    How would a tech know if the data is stable/sampled or not stable/not sampled?
     
  6. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    User willwatts has started five threads within the past few hours. I am closing all of them temporarily.
     
  7. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    We (moderators) agreed to reopen one of "willwatts"'s threads, and he chose this one.

    So this thread is now open again.
     
  8. hevans1944

    hevans1944 Hop - AC8NS

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    If you have a two-channel o'scope you can use one channel to both trigger the horizontal sweep and display the edge of the clock signal. You need to have a fast enough sweep to see the interval a few nanoseconds after the clock edge. A delayed sweep is often helpful if it allows the clock edge to be displayed in the middle of the screen with the data transitions on either side. Ideally, all data transitions will occur well before (by at least the setup time) the clock edge that cause the device to change state and will remain stable until after the hold time specification.
    Yes, you probe whatever input for which you want to verify the data setup and/or hold time.
    If the data is changing before, during, or after the clock edge, in a time interval less than the published setup and/or hold times, then the data fails to satisfy the device setup and/or hold time specifications. Depending on the device and other factors, such as supply voltage and operating temperature, a device could operate satisfactorily without the data meeting the minimum setup and hold times, but it is poor engineering to depend on that fortuitous combination.

    I should mention these measurements are not easy to make or evaluate, depending on the specific logic circuit being evaluated. The main reason for performing the measurements is to troubleshoot a logic circuit that is failing to operate as planned. This means the "data" may not be changing in a consistent, repeatable, manner. There could be thousands or millions of clock cycles without an error until an unplanned race condition causes a setup or hold time error. It is not a troubleshooting task I would put upon a novice technician, i.e., someone who asks the kind of questions you ask.

    I have troubleshot digital logic using just a logic probe, a schematic diagram, and my own reasoning of how a circuit should work, while at the same time trying to visualize what could go wrong to make it fail to work. This skill is only acquired by probing actual circuits, not by asking questions on a forum or reading about it in a text book. Very complicated digital circuits, such as microprocessors, require more sophisticated tools such as logic analyzers and multi-function oscilloscopes to troubleshoot effectively.
     
    Last edited by a moderator: Nov 16, 2014
  9. willwatts

    willwatts

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    Nov 15, 2014
    The Clock circuit output and the data source have to be offset in time, not in sync and not aligned edge to edge for it to have a setup time and hold
    time?

    Because if the data signal and clock signal were aligned leading edge to leading edge there will be not setup time or hold time right?

    I'm still confused how a circuit or design sets up the setup times and hold times for each stage or section of the circuit, the designer must use delay networks in the PATHS of the data signal and clock signal
     
  10. willwatts

    willwatts

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    Nov 15, 2014
    I mean the "Relationship between" the clock signal and date signal have to be offset in time, delayed time duration interval , out of sync, not aligned together in unison

    Measuring the Time interval Relationship: there is a delay in time , time interval
    When you measure the Time interval of the Relationship between the Clock signal and data signal

    If the Data signal is "during" the clocks edge , that means they are in sync and aligned together in unison which will give you a set up and hold time Error right?
     
  11. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Setup and hold times are a feature of the device and must be allowed for in the signal, not the other way around.

    The signal (and I am including the clock here as a signal) must provide for the setup and hold times of the device.

    Your original question was about measuring these. Did you mean measuring the setup and hold time of the device (which has been pointed out to you is generally something that comes from design and for an C will be found in the datasheet) or the provision for setup and hold times as provided by the signal timing?
     
  12. willwatts

    willwatts

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    By the signal timing? measuring the setup and hold times in a REAL circuit

    I have my oscilloscope turned on , where do I probe , how do I set up the Oscilloscope to measure the setup times and hold times, do i use the storage section and set my time base to 1 second or 5 seconds? or do i use the delay B sweep and set my time base to what if the logic signals are in nanoseconds.

    I'm also asking how does a designer know how to set the clock signal to PROVIDE the setup and hold times or how does the data signal MEET and occur at the correct and right timing for the setup time and hold times?
     
  13. willwatts

    willwatts

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    Nov 15, 2014
    the datasheets tell the designer the data signal and clock signal need to "occur" at a range. But the designer needs to provide that the clock signal and data signal are both going to "occur" at the right times or you will have a setup time and hold time error.

    If The Data signal happens to "occur" during the clock signals edge which will cause a setup time and hold time error. My question is what does the designer do? add delay networks in the data signal path?
     
  14. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    Right. The device will misbehave because the signals have violated its setup and/or hold time requirements.
    Sometimes, yes.

    Sometimes signals can be synchronised with other signals by passing them through a logic element such as a D flip-flop, whose output can only change at defined times, which are controlled by some other signal such as a clock signal. Passing the signal through a clocked D flip-flop will delay and synchronise it, so that it is guaranteed (assuming no metastability - but let's not open that can of worms yet) to be stable during certain time periods; this can ensure that the device's setup and hold requirements are always met.

    Which method is best depends on the specific details of the device and the circuit - the actual setup and hold requirements, and the worst-case timing relationships between the existing signals.
     
  15. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    You can't measure setup and hold times like this. What you can do is measure the the times you have allowed for setup and hold. The chip might require a setup time of 4ns, and your circuit gives it 3 days -- that doesn't measure the setup time, it measures that you have allowed for a setup time of less than 3 days. Id you measured it ans saw 3.5ns then you would conclude you had not given it sufficient setup time.

    You need to understand the difference between the setup time (which is largely fixed for a given chip determined by the propagation delays in the logic) and the signal timing itself.

    1) Do you understand propagation delay and how it might affect setup and/or hold times? You should read this. (And read it until you understand it).

    It is like making a cup of coffee. The cup contains a certain amount of water. How much water do you put in the kettle? Clearly you put in the required amount or more. It's the responsibility of the person making the coffee to fill the kettle with enough water, and the amount you put in does not actually measure the capacity of the cup. In fact if you don't know the capacity of the cup (maybe you haven't chosen a mug yet) you need to put more water in the kettle than the maximum size of the mug you might choose. This analogy breaks down with a cup of coffee because when we pour the water into the cup we can see that it is full and stop (thus providing exactly enough water). For a circuit, we cannot tell exactly when it is set-up, and have to rely on the maximum time it might take (just as if in the coffee case, we had not yet chosen a mug).

    2) Do you understand the coffee analogy, and the importance of not having chosen a mug?

    For an input with a setup time, we can't know when i is set up. We must provide as least the maximum time.

    You may be familiar with "overclocking" computers. By default the memory timing is set up for the worst case. Many of these settings are related to the setup and/or hold times of the memory. You can fiddle with these, reducing the time allowed until your computer runs as fast as possible without crashing. Here you are deliberately reducing the signal timing below the maximum setup times. At some point you will reduce them below the actual set-up time for the chip, and the computer crashes. If you can get timing greater than the actual setup times, and less than the default (typically maximum or greater) then your computer runs faster. You are also in the twilight zone where the computer is no longer guaranteed to work.

    BUT, you have not measured the actual setup or hold times, just found some values which work.

    3) Do you understand that the process of overclocking a chip may involve timings less than the maximum setup (or hold) times, but greater than the actual setup (or hold) time for that particular chip?

    4) Do you understand that in the above case you are doing the equivalent of putting less and less water in the kettle until you no longer have enough to fill the mug, and that the same amount of water might fail for another mug?

    The data doesn't "occur". It might change during the setup or hold times.

    Please answer questions 1 to 4 above so I am certain you understand.
     
  16. willwatts

    willwatts

    106
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    Nov 15, 2014
    1) Do you understand propagation delay and how it might affect setup and/or hold times?

    Propagation delay it how long it takes for the logic signal to pass through the logic IC chips from input to output.

    The Propagation delay causes the Set up times and hold times to either be positive or negative, "it shifts the timing"

    2) Do you understand the coffee analogy, and the importance of not having chosen a mug?

    No I don't get it this analogy

    For an input with a setup time, we can't know when i is set up. We must provide as least the maximum time.

    Ok the data sheets lets say 4nS setup time and 6nS hold time
    how do i Provide this? how does the clock provide 4nS setup time and 6nS hold time , how does the data signal provide it too?

    3) Do you understand that the process of overclocking a chip may involve timings less than the maximum setup (or hold) times, but greater than the actual setup (or hold) time for that particular chip?

    That doesn't make sense

    You're saying that when you increase the timing speed, the setup and hold times will decrease in time?

    4) Do you understand that in the above case you are doing the equivalent of putting less and less water in the kettle until you no longer have enough to fill the mug, and that the same amount of water might fail for another mug?

    Yes if you decrease the timing speed of the clock , the setup and hold times will decrease in time
     
  17. willwatts

    willwatts

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    Nov 15, 2014
    If i print out the data sheets for flip flips , registers, and look up the set up times and hold times. The problem is how do you provide the data signal and clock signal to arrive and occur at the right time?

    Does it really matter if the data signal and clock signals timing relationships are positive , negative or zero holding times and setup times?

    I thought to measure the setup times and hold times I had to set my Oscilloscope up for single shot triggering to capture the event. Then you compare the setup time and hold time measured to the datasheets of that IC chips you're measuring under test.
     
  18. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    You have not answered my questions above Danny.

    I won't answer your questions until you do some work yourself.
     
  19. hevans1944

    hevans1944 Hop - AC8NS

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    I think we may be focusing our attention too narrowly on clock pulse transitions versus data stability before and after the clock transition. This is usually not a problem unless the design logic is faulty or a component has failed. In the case of component failure, finding the failure almost never requires measuring setup and hold times. In the case of faulty logic design, the technician must first prove this and then pass the buck up-stream to the design authority.

    The broader view is: how do state machines operate? There are several considerations to be made in designing a synchronous state machine, which is the only state machine requiring a clock. The speed of the clock and the propagation delay through the logic are the primary design parameters. A broad overview can be found in the attached PDF file. It is really a lot more complicated.

    Where the stuff really hits the fan is trying to accommodate asynchronous inputs from real-world devices that know nothing about the clock. Data inputs from asynchronous devices can change at any time. This means setup, and possibly hold times, are guaranteed to be violated at some unpredictable time. One possible way to solve this problem (and it is a very difficult problem to solve) is to synchronize the data presentation with the system clock by storing the data state in an RS flip-flop and later clocking the stored data out. A device that purports to do this is the SN74120 Dual Pulse Synchronizer. There may be others. Note that data setup and hold times must still be observed if the data is to be valid on the next clock pulse. I used this device in the 1970s to synchronize operator inputs with state machine logic, but today I would use software to perform the synchronization function.
     

    Attached Files:

  20. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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