Logic family selection

[Sravanthi]

Hi...

I am designing a circuit, there I have a requirement, AND gate open input should be considered as logic low and when one of the input is logic low other input shouldn't be passed to output.
To treat open input as logic zero, I have selected PECL(Positive Emitter Coupled Logic).
In 2 input AND, if one of the transistor fails at short then other input will be passed to output.
So when one of the input is open and corresponding transistor is failed at short mode then other input is passing to output.

To avoid this,any other logic family can I use or is there any other solution.

 

[GPG]

Choose a CMOS family. Put a large value resistor to ground from the floating input.
Then I have to ask why?

 

[Sravanthi]

Choose a CMOS family. Put a large value resistor to ground from the floating input.
Then I have to ask why?

Thank you for immediate reply...
In my application open input may come because of some failure.
Always 2 inputs will be connected to gate.
So can you suggest me some solution.

 

[BobK]

GPG just did give you a solution, why are you asking again?

Bob

 

[Sravanthi]

Choose a CMOS family. Put a large value resistor to ground from the floating input.
Then I have to ask why?

Please explain this point clearly.
Pull down resistor makes floating input to give AND output as zero.
But how this makes AND gate output as zero when transistor fails in short.

 

[GPG]

Which transistor? Perhaps you should show circuit.
And why use (P)ecl? there are more options in other families.

 

[Sravanthi]

Which transistor? Perhaps you should show circuit.
And why use (P)ecl? there are more options in other families.

Thank you for reply.
I think my question is not clear to you.
So I am explaining here ...
I want to implement a 2 input AND gate with some requirements
1. When open input comes output should go to zero. (Open will come with some failure,otherwise always 2 inputs will be connected)
2. The component, (eg. transistor or MOS) which takes input fails in short/open, output should goes to logic zero.

With these can you please suggest me a solution.

Thank you in advance...

 

[AnalogKid]

1. A resistor to GND will pull the input low if its normal drive signal goes to an open circuit. This will force an output state of 0.

2. If you are asking about a transistor failure *inside* the AND gate, there is no way to predict how that will affect the output, and no way to force the output to 0 when it happens. Why do you need this capability?

ak

 

[Sravanthi]

1. A resistor to GND will pull the input low if its normal drive signal goes to an open circuit. This will force an output state of 0.

2. If you are asking about a transistor failure *inside* the AND gate, there is no way to predict how that will affect the output, and no way to force the output to 0 when it happens. Why do you need this capability?

ak

Thank you for reply....
Instead of using existed AND gate IC does is it possible to construct our own circuit with these requirements.

 

[AnalogKid]

Yes, and it might be pretty simple if you give up some information. Make that ANY information. 5 posts and almost zero technical details....

What are the two driving signals you want to AND? What kind of circuit produces them? Are they digital signals,or analog signals that just happen to be within a digital logic voltage range? What is the voltage range for a logic 0? What is the voltage range for a logic 1? What is the output impedance of the drivers? What are the frequencies of the signals? What are the minimum pulse widths?

What does the AND circuit output drive? What are the voltage level requirements for logic 0 and logic 1? What are the current requirements? Does whatever this circuit drives require a symmetrical driving point impedance?

An AND circuit could take 3 parts or 20 parts. Without some design parameters, we'll never know.

ak

 

[Sravanthi]

Yes, and it might be pretty simple if you give up some information. Make that ANY information. 5 posts and almost zero technical details....

What are the two driving signals you want to AND? What kind of circuit produces them? Are they digital signals,or analog signals that just happen to be within a digital logic voltage range? What is the voltage range for a logic 0? What is the voltage range for a logic 1? What is the output impedance of the drivers? What are the frequencies of the signals? What are the minimum pulse widths?

What does the AND circuit output drive? What are the voltage level requirements for logic 0 and logic 1? What are the current requirements? Does whatever this circuit drives require a symmetrical driving point impedance?

An AND circuit could take 3 parts or 20 parts. Without some design parameters, we'll never know.

ak

Thank you for helping me in this regard
I will answer your queries
1. Pulse transformer (IT237 IC), with pulse ON duration of 40μs and OFF duration of 140μs pulse output has to drive the AND gate.(http://www.mouser.com/ds/2/355/DS_IT-single_series_20110616_web35_01-10035.pdf)
2. AND circuit output has to drive the TTL OR gate.
Here I am attaching the part of my design.
Please ask if any further clarifications are needed.

 

[AnalogKid]

What are the power supply voltage and logic family of the OR gate?

ak

 

[Sravanthi]

What are the power supply voltage and logic family of the OR gate?

ak

Thank you for reply...
Its 5V and TTL logic family. (IC number SN 74HCT32)

 

[AnalogKid]

Any digital logic part with HCT in the number is *not* TTL. It is a CMOS part with TTL-equivalent transition levels but with the super-high input impedance of CMOS.

Because the signal source has a wildly asymmetrical output impedance and cannot sink any current, this is not going to be the 3-component solution. What is the purpose of the diode connected to the transformer secondary?

ak

 

[Sravanthi]

Any digital logic part with HCT in the number is *not* TTL. It is a CMOS part with TTL-equivalent transition levels but with the super-high input impedance of CMOS.

Because the signal source has a wildly asymmetrical output impedance and cannot sink any current, this is not going to be the 3-component solution. What is the purpose of the diode connected to the transformer secondary?

ak

Thank you for helping me to solve this problem...
I have a requirement to the OR gate as open input(This may happen with some failure to the input eg like PCB track cut) should be considered as logic high. So with this I want to select TTL OR gate.
Pulse transformer is giving negative spike, to protect AND gate input circuitry diode is placed at secondary of pulse transformer.

 

[AnalogKid]

The language translation is not going well, so lets discuss each gate individually.
If the requirement is that each OR gate input go to a logic 1 if there is a trace cut, this can be done with a pull up resistor located very near to each OR gate input. Is this an acceptable solution for this requirement?

ak

 

[AnalogKid]

Going back to your schematic in post #11, that is a very strange way to produce a galvanically isolated pulse. Is it possible to substitute an optocoupler for the transformer? If so, the entire AND gate function can be performed with one resistor.

ak

 

[Sravanthi]

Going back to your schematic in post #11, that is a very strange way to produce a galvanically isolated pulse. Is it possible to substitute an optocoupler for the transformer? If so, the entire AND gate function can be performed with one resistor.

ak

Pulse transformer is used not for isolation. Its used for some other purpose.So i cant remove.

 

[Sravanthi]

The language translation is not going well, so lets discuss each gate individually.
If the requirement is that each OR gate input go to a logic 1 if there is a trace cut, this can be done with a pull up resistor located very near to each OR gate input. Is this an acceptable solution for this requirement?

ak

This is acceptable...
Is there any disadvantage in using TTL, which treats open input as logic 1.

 

[AnalogKid]

Is there any disadvantage in using TTL, which treats open input as logic 1.

Yes, the fact that you cannot rely on an open TTL input to float to a high condition. It floats high by accident, not by design. It is a relatively high input impedance condition, and radiated noise can cause the input to transition. For any logic family at any time, never leave an input floating.

ak