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Logic design help needed

Discussion in 'Electronic Design' started by Bubba Jones, Mar 1, 2004.

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  1. Bubba Jones

    Bubba Jones Guest

    I need a simple circuit to produce the following logic levels in
    sequence

    Clk A B
    ---- --- ---
    1 0 0
    2 0 1
    3 1 1
    4 1 0
    5 0 0
    6 1 0
    7 1 1
    8 0 1
    9 0 0

    Clk sequence 1 to 5 must be in order and can be independent of
    sequence 5 to 9. I may need to run sequence 1 to 5 for about 20
    iterations and then run sequence 5 to 9 for about 20 iterations.

    I know I can do this with a PIC or with a binary counter and Eprom to
    define logic, but would like to be able to do it with counters and
    simple gates

    Any ideas???


    Logically challenged,
    Bubba
     
  2. CBarn24050

    CBarn24050 Guest

    try rewriting this post so it makes sence, then someone will tell you how to do
    it.
     
  3. mikem

    mikem Guest

    I think we can generate your logic with a "state machine", which has
    two inputs (Mode and Clock), and two outputs, your A and B (not counting
    Vss and ground).

    Clock tells your state machine when to change state...

    Mode tells your state machine if you want it to produce states 1-5, or
    states 5-9.

    A and B are your outputs, which are are defined per your table.

    There are five states numbered 1-5; and five more numbered 5-9,
    inclusive. Since both modes have exactly five states, we can
    build just one state machine that has exactly five states, and the Mode
    input can select two ways of decoding the internal states to produce the
    two diffent patterns at A and B.

    My favorite way of making state machines is the "Johnson" counter.
    We need one which will count through five states. I have attached
    an LTSpice schematic which implements a five-state machine which
    directly counts in the patterns you want. It takes three flip-flops to
    make five states. One AND gate short cycles what would naturally be a
    six-state Johnson counter to make it recyle at the fifth state.

    My design is attached as an LTSpice text file. Save everthing below the
    ___________________________ line into a file called "StateMachine.asc"
    and then open that file with LTSpice. You can download a free copy of
    LTSpice from Linear Technology.

    www.linear.com/software

    I have labelled the three flops X, Y and Z. Run the LTSpice simulation
    and look at V(x), V(y), and V(z) vs Clk. Note that if you want your
    1-5 sequence, then A=X and B=Y, directly with no decoding.
    If you want states 5-9, then A=Y and B=X. Now all you need is some
    simple combinatorial logic (gates only) with inputs X, Y, and Mode, and
    with outputs of A and B.

    Before I can tell you how to do the decode, I need to know when the
    "Mode" signal changes relative to the internal states of X, Y and Z? If
    you tell me that Mode could change asynchronously (at any time), and you
    expect the state machine to finish the current 1-5 or 5-9 sequence
    before going to the opposite seqence, then it would take adding one more
    flop to synchronize "Mode". Write back with that spec.

    Dr MikeM

    ___________________________________________________________________________

    Version 4
    SHEET 1 880 680
    WIRE -1136 -112 -1088 -112
    WIRE -1392 -112 -1296 -112
    WIRE -1296 -64 -1360 -64
    WIRE -1360 0 -1344 0
    WIRE -1056 -64 -992 -64
    WIRE -496 -224 -1488 -224
    WIRE -1360 192 -1360 224
    WIRE -1360 112 -1360 0
    WIRE -1360 -64 -1360 0
    WIRE -1056 -64 -1056 0
    WIRE -992 -112 -1088 -112
    WIRE -1056 0 -736 0
    WIRE -736 0 -736 -64
    WIRE -736 -64 -704 -64
    WIRE -832 -112 -800 -112
    WIRE -800 -112 -704 -112
    WIRE -528 -64 -496 -64
    WIRE -496 -64 -496 -224
    WIRE -544 -112 -448 -112
    WIRE -1344 0 -1056 0
    WIRE -816 -64 -768 -64
    WIRE -768 -64 -768 -208
    WIRE -768 -208 -1472 -208
    WIRE -1472 -208 -1472 -128
    WIRE -1472 -128 -1456 -128
    WIRE -1456 -112 -1488 -112
    WIRE -1488 -112 -1488 -224
    FLAG -1360 224 0
    FLAG -800 -112 Y
    FLAG -448 -112 Z
    FLAG -1088 -112 X
    FLAG -1344 0 Clk
    SYMBOL Digital\\dflop -624 -160 R0
    WINDOW 3 -124 -24 Left 0
    SYMATTR InstName A1
    SYMATTR Value Trise=100u
    SYMBOL voltage -1360 96 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    WINDOW 3 43 58 Left 0
    SYMATTR Value PULSE(0.1 0.9 0.5m 1u 1u 0.5m 1m)
    SYMATTR InstName V2
    SYMBOL Digital\\dflop -912 -160 R0
    WINDOW 3 -128 -21 Left 0
    SYMATTR Value Trise=100u
    SYMATTR InstName A4
    SYMBOL Digital\\dflop -1216 -160 R0
    WINDOW 3 -124 -21 Left 0
    SYMATTR Value Trise=100u
    SYMATTR InstName A5
    SYMBOL Digital\\and -1424 -160 R0
    SYMATTR InstName A2
    TEXT -1314 202 Left 0 !.tran 15m
    TEXT -1088 40 Left 0 ;Divide by 5 Johnson Counter.
    TEXT -1200 80 Left 0 ;X and Y count in the cadence shown in the table.
     
  4. Jim Thompson

    Jim Thompson Guest

    Looks to me to be nothing more than a 2-bit UP/DOWN counter in Gray
    code.

    ...Jim Thompson
    --
    | James E.Thompson, P.E. | mens |
    | Analog Innovations, Inc. | et |
    | Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
    | Phoenix, Arizona Voice:(480)460-2350 | |
    | E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
    | http://www.analog-innovations.com | 1962 |

    "Will you love me when I'm sixty-four?"
     
  5. George

    George Guest

    Assuming 1,5,9 represent the same step, i.e. the 0,0 state is the
    beginning/end of the sequence, I (a 2nd year EE student) can do it
    with 4 AND gates, two OR gates, one inverter, 3 Flip Flops, and a
    counter circuit that counts to 20. For your first sequence,
    A(next)=B(current) and B(next)=/A(current). For the second,
    A(next)=/B(current) and B(next)=A(current). The counter circuit should
    reset at 20, which flips a second flipflop from low to high(T type,
    can do it easily using a D type). This second flipflop is the control
    signal for the logic gates. If it is low, it causes the first
    sequence, if it is high it causes the second sequence.The logic gates
    simply select which outputs to input. I don't have an ASCII schematic
    program, so this is the best I can do to show you.
    Input to flip flop A: Two AND Gates connected to an OR gate
    connected to input of A. The AND gates are connected to: 1st AND gate:
    control signal (low is first sequence) and Output of B. 2nd AND gate:
    inverted control signal and inverted Output of B (use the inverter to
    invert the control signal, flipflop B should have an inverted output).
    Input to flipflop B: same arrangement. 1st AND gate: control signal
    and inverted Output of A. 2nd AND gate: inverted control signal and
    regular output of A.
    This will cause your signal with the regular outputs of flipflops
    A and B being the respective outputs you asked for. All you need for
    the counter circuit is any 5 bit or greater binary counter or two
    decimel counters. You need a reset pin on the counters if you are
    going to use binary counters though. Just have the 20th output
    connected to the reset pin(if using binary) and to the control signal
    flipflop.
    I'm sure more experienced people could probably do it with less,
    but 7 gates, 3 flipflops, and a counter is not bad for me.
    George
     
  6. George

    George Guest

    Oh yeah, to go with my previous message, to have a D flipflop act
    like a t flipflop, just tie /D (inverted output) to the input and have
    the pulse from the counter enter the clock.
     
  7. GPG

    GPG Guest



    A B

    | |
    .------------. | |
    | | | |
    | 0 o | |
    | | | |
    | 1 o | |
    | | | |
    | 2 o-------------------->|-|
    | 4017 | | |
    | 3 o--|-->|-----| |
    | | |----------------->|-|
    | 4 o----->|-----| |
    | | | |
    | 5 o | |
    o CK | | |
    | 6 o----->|-----| |
    | | | |
    | 7 o--|-->|-----| |
    | | |----------------->|-|
    | 8 o-------------------->|-|
    | | | |
    | 9 o---. | |
    | | | | |
    | RS | | | |
    '-------o----' | | |
    | | | |
    '--------' .-. .-.
    | | | |
    | | | |
    '-' '-'
    |GND |GND
    created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
     
  8. Jamie

    Jamie Guest

    yeah, just get a 1 of 10 multiplexer or 1 of 10 serial shift reg and use
    Diodes on the 1 logic lines to lift a pull down resister that is on
    both A B output points.
    looks to me like your running some kind of sequencer ?
    if you can not find a 1 of 10 there are 1 of 16 multiplexers.
    you just don't need to use all of the lines. the #10 line can be used
    to reset the count back to 0.
    hope that gives you some ideas..
     
  9. It can be done with one 74HC153 dual 4-1 multiplexer and a 74HC74 dual
    D-type flipflop. I hesitate publishing the circuit here because you
    might want to try yourself. Hint: A 4-1 multiplexer can realize any
    logic function with 3 inputs and 1 output (you may possibly need an
    extra inverter, but if you're clever you can make use of the inverting
    output of one of the flipflops).

    This is a solution that does not use basic gates, of course, if that's
    what you wanted.
     
  10. John Fields

    John Fields Guest

    ---
    Yeah, but first some questions.

    You say you want the 1 to 5 sequence to repeat, but it's not clear
    whether you want this:

    1 0 0
    2 0 1
    3 1 1
    4 1 0
    5 0 0
    1 0 0
    2 0 1
    3 1 1
    4 1 0
    5 0 0
    ..
    ..
    ..

    or whether you want this:

    1 0 0
    2 0 1
    3 1 1
    4 1 0
    1 0 0
    2 0 1
    3 1 1
    4 1 0
    ..
    ..
    ..

    Likewise with 5 to 9.

    Do you want this:


    5 0 0
    6 1 0
    7 1 1
    8 0 1
    9 0 0
    5 0 0
    6 1 0
    7 1 1
    8 0 1
    9 0 0
    ..
    ..
    ..

    or do you want this:

    5 0 0
    6 1 0
    7 1 1
    8 0 1
    5 0 0
    6 1 0
    7 1 1
    8 0 1
    ..
    ..
    ..

    ???
     
  11. Bubba Jones

    Bubba Jones Guest

    Thanks to all for some great ideas!


    I should have been clearer on what I am trying to do.

    I wish to interface to a serial mouse controller chip

    http://mechatronics.me.vt.edu/DataSheets/dsheets/assp/40101C.pdf

    to simulate mouse movements.

    The purpose of this is to keep a Citrix client session active while
    batch billing processing occurs on an SQL server. This will allow the
    session to not close based on lack of mouse movements, and will
    relieve a user from being attentive to computer (up to 4 hours).

    I would like to house circuit in the mouse. So, keeping part count
    down is appealing.

    I figure a 555 timer will be fine for clock source with about 10
    movements forward and then 10 movements backward should suffice.

    Data sheet appears to indicate need to start at 0 0 and end at 0 0 for
    each movement cycle.

    I may experiment with counter & eprom to define logic and then migrate
    design to J/K flip lops and gates after logic states proven with mouse
    controller chip.


    Bubba
     
  12. Active8

    Active8 Guest

    yeah. states 0-5 and 9-5 are mirrors. would be doable with an LFSR
    if a two stage LFSR had a mirror and spit out that sequence.

    Notice that the A & B states are just time shifted one way for 0-5
    and the other for 9-5.
     
  13. Jim Thompson

    Jim Thompson Guest

    See "TwoBitUpDownGrayCounter.pdf" on the S.E.D/Schematics Page of my
    website.

    ...Jim Thompson
    --
    | James E.Thompson, P.E. | mens |
    | Analog Innovations, Inc. | et |
    | Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
    | Phoenix, Arizona Voice:(480)460-2350 | |
    | E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
    | http://www.analog-innovations.com | 1962 |

    "Will you love me when I'm sixty-four?"
     
  14. GPG

    GPG Guest

    ..---------. .----------.
    | | | |
    | Q4 o--------------------------------o S0 |
    | | | |
    | Q5 o--------------------------------o S1 |
    | | | |
    | | GND o X0 |
    | | | X o--- A
    | 4060 | GND o Y0 |
    | | | |
    | | V+ o X2 |
    | | | |
    | | V+ o Y2 |
    | | | 4052 |
    | Qx o-----o-------------------o------o X3 |
    | | | | | Y o--- B
    '---------' | '------o Y1 |
    | |\ | |
    '-------| >O--------o------o X1 |
    |/ | | |
    '------o Y3 |
    | |
    o |
    | |
    o |
    | |
    '----------'
    created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de
    This automatically reverses after a number of cycles depending
    on the connection of Qx. Reversing occurs when A=B=0.
    Inverter can be opamp.
     
  15. GPG

    GPG Guest

    Forgot to mention, 4060 has own osc.
     
  16. GPG

    GPG Guest

    "Will you still love me,
    will you still love me
    when I'm sixty-four?"
     
  17. John Fields

    John Fields Guest

     
  18. Bob Stephens

    Bob Stephens Guest

    not even close
     
  19. John Fields

    John Fields Guest

     
  20. Bob Stephens

    Bob Stephens Guest

    Oh well, no good deed goes unpunished. I was *agreeing* that >>>is incorrect.

    Bob
     
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