Z
Zerrin
- Jan 1, 1970
- 0
I am using a Lattice ispMACH 5000VG CPLD (LC51024VG) on my design.
I am very frustrated with the result of the IspLever V3.0 development
Tool.
Stalled in the same place as two months ago. No progress in 2 months.
Project cancellation iminent. Unable to make any changes with
predictable, dependable results, despite every possible design
workaround imagineable attempted. Over 42 different workarounds
attempted, including registered mux outputs, straight binary TS
counter chain, 5-way reduced to 3-way mux, etc.,etc.
Total extent of changes implementable in two months without
unpredictable side effects (like complete breakdown in logic
functionality - not timing) are 3 x D registers, 3 x 2-input
and-gates,1x 3-input nor gate and 1x2-input nand gate.
Thats it. No other changes could be made with expected behavioral
effects.
Is anyone else having same problems or just me? Need an advise from
experts.
Regards,
Zerrin
I am very frustrated with the result of the IspLever V3.0 development
Tool.
Stalled in the same place as two months ago. No progress in 2 months.
Project cancellation iminent. Unable to make any changes with
predictable, dependable results, despite every possible design
workaround imagineable attempted. Over 42 different workarounds
attempted, including registered mux outputs, straight binary TS
counter chain, 5-way reduced to 3-way mux, etc.,etc.
Total extent of changes implementable in two months without
unpredictable side effects (like complete breakdown in logic
functionality - not timing) are 3 x D registers, 3 x 2-input
and-gates,1x 3-input nor gate and 1x2-input nand gate.
Thats it. No other changes could be made with expected behavioral
effects.
Is anyone else having same problems or just me? Need an advise from
experts.
Regards,
Zerrin