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(Last) Burst, (Last) Single Data Transfer

Discussion in 'Electronic Basics' started by Simone Winkler, Aug 17, 2003.

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  1. Hey!

    Can somebody explain me, what this exactly means? i'm doing a serial
    interface that has a lot of options, as e.g. asynchronous OR synchronous
    transfer.

    and there is the possibility to set these DMA/IRQ options - i don't really
    know what it should mean, except that "burst" refers to a transfer of more
    data at once, whilst "single" always just means a transfer of a single
    bit/byte/...

    thank you!
     
  2. You have a tiger by the tail there Simone.

    Asynchronous serial communications uses fixed bit timing with word preamble
    and postamble (typically, start and stop bitd) and does not send a clock
    signal along with the data.

    Synchronous serial communications (HDLC, etc) uses a clock signal the is
    either generated or received by the USART.

    The difference between the two is significant. What kind of media is being
    used? RS232? If so, then you want asynchronous.

    DMA:
    Direct Memory Access. You can transmit data out your USART by writing values
    to a register, which is sometimes used, but is inefficient if your CPU has
    other things to do, especially at high serial bit rates. The alternative is
    to program a device callled a DMA controller to do the writting (and
    receiving) for you. Its complex though, requiring proper initialization of
    the USART, DMA controller, and memory spaces. The CPU writes a data pattern
    to a memory block and then tell the DMA controller to begin transmitting. It
    feeds the memory block to the USART as the required pace.

    IRQ
    Interrupt Request. Your USART can probably be programmed to issue a hardware
    interrupt when either the transmitter or receiver needs attention or a comm
    error has been detected. The interrupt causes an Interrupt Service Routine
    to be executed, designed to handle the USART. Or, the DMA Controller can
    also be programmed to issue an interrupt when a block of data has been
    received or transmitted. Again, an ISR will sevice the DMAC and keep it feed
    with data, etc. In all cases the hardware interrupt subsystem must be setup
    to recognize and handle the interrupts issued by these devices.

    Tired yet?

    The USART probably also has optional FIFOs that allow for the preloading of
    transmity data and storae of receive data. Thats another level of
    complexity.

    Bursting.
    Bursting is a term that simply means to transfer two or more words of data
    back-to-back, ie: no delay between transfers.

    Hope this helps.
    Dana Frank Raymond
     
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