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Karnaugh Map Problem

Discussion in 'Electronics Homework Help' started by Bondo86, Jan 18, 2014.

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  1. Bondo86

    Bondo86

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    Oct 10, 2012
    I'm not sure if anyone's familiar with Project Lead the Way or not, but there's a problem in it(2.2.5) that uses four sensors on a fire place and three out of four must have a 1. If not it signals a zero.

    Here is the Karnaugh Map I created below.
    [​IMG]

    From that I think my logic is, BCD+ACD+DAB+CAB

    If someone could check my work I'd appreciate it. Thanks, Bondo86.
     
  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    That seems fine
     
  3. Bondo86

    Bondo86

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    Oct 10, 2012
    Thanks, I wasn't real sure because of the way they intersected like that.
     
  4. Laplace

    Laplace

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    Apr 4, 2010
    You should do the Karnaugh minimization visually; it's the only way to be sure.
    [​IMG]
     

    Attached Files:

  5. Bondo86

    Bondo86

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    Oct 10, 2012
    Thanks Laplace. I downloaded a program called Logical Circuit from logiccircuit.org and I built the circuit using the logic shown and the truth table came out perfect. I was told I only could use NAND logic to complete the circuit, and it took me 33 gates to do so. HERE is a picture of it. Can anyone see a way to reduce the number of gates? My instructor told me I'd be able to complete it with three 7400's which only gives me 18 gates to work with. I think he was guessing though. (He's pretty laid back)

    This homework is from Project Lead the Way 2.2.5 if anyone is familiar. Thanks for any help.

    Edit: Sorry for the sloppy picture. It's hard to make connections in that program.
     
    Last edited: Jan 19, 2014
  6. Laplace

    Laplace

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    184
    Apr 4, 2010
    It is possible to minimize by 4 squares at a time instead of two, in this case by collecting the zeroes instead of the ones. But then the final result must be complemented. This also leads to a design implementation suitable for NOR gates since the inputs will not need to be negated.
     

    Attached Files:

  7. Bondo86

    Bondo86

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    Oct 10, 2012
    Unfortunately this home work requires me to use NAND gates only. With NANDs that puts the gate count at 33 and 48 using NOR. I was excited for a second lol. I did study what you said however and your post is obviously going to be useful in the future seeing that NAND, and NOR are the norm for TTL, and CMOS. To the favorites tab lol. Thanks for the help.
     
  8. Laplace

    Laplace

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    184
    Apr 4, 2010
    I can't understand why you would need so many gates. The most I would use is 19 NAND gates. Are you not using a negative logic implementation? Here is what I would do:

    Take the 6 term Sum of Products (SOP) expression from above and lay it out in a pure logic diagram using only OR, AND, & NOT gates. Then convert it to negative logic by adding inversion pairs to the signal lines, keeping in mind that a negated output AND gate is the same as a negated input OR gate and a negated output OR gate is the same as a negated input AND gate. So if your ultimate goal is to use NAND gates you will want all the gates on the negative logic diagram to be either negated output AND gates or negated input OR gates, plus as many inverters as necessary. Then convert the negative logic diagram to a physical implementation using just NAND gates.

    I have attached the pure logic and negative logic diagrams that I used but you will need to do the physical gate implementation yourself.
     

    Attached Files:

  9. Bondo86

    Bondo86

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    Oct 10, 2012
    You've been a great help. As you can see I'm pretty new to logic. Funny story, this is work I was doing over the weekend, and when I got back to school I told my instructor that I needed 33 NAND gates to get it to work, and I could tell he about started laughing at me. Before I was able to read your post I put the logic in MultiSim, and it outputted the gates for me. Kind of cheating, but it showed me I only needed 17 NAND gates. So I guess I was a was off with 33. I definitely need to try to figure out how to complete this using the process you showed me, or what will I learn?

    HERE's a picture from MultiSim. The top right is the circuit using only NAND logic, and the top left is the same logic using AND OR. The bottom is something from another circuit.

    When I get home I'll try writing this out on paper, and maybe you could help me check it. I'm in the computer lab right now without my paper and pencil.

    Thanks for the help, Jarod.
     
    Last edited: Jan 20, 2014
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