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JTAG problems

Discussion in 'Electronic Design' started by [email protected], Jul 12, 2007.

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  1. Guest

    Hello every one,
    We have designed a board which
    contains an ALTERA fpga and an EPROM(EPC2LC20).The design is done with
    respect to some existing reference schematics.We have populated our
    PCB so as to get the power to all the components and then we have
    placed the components making up the JTAG circuitary along with the
    FPGA and EPROM.
    ,Altera's Byte blaster is being used
    which is working fine. have checked all the circuitary which seems to
    be alright but we keep getting the error"Unable to access the JTAG
    chain".We have also tried the steps in the ALTERAs trouble shooters.
    Do we need to proceed in a different
    way while programming the chip/EPROM for the first time.And also what
    is the passive serial mode in the Quartus tool for programming. Any
    help would be highly appreciated.Thanks in advance.
  2. Ben Jackson

    Ben Jackson Guest

    Since that's an obsolete config device you should probably mention
    which obsolete FPGA you're configuring with it. Configuration has
    evolved quite a bit.
    I just did the layout for a board with a FLEX 6000 (obsolete but free),
    so I happen to know that you can't program them via JTAG (they do support
    boundary scan, which is probably not what you want), which brings me to
    your final question:
    Passive serial is how you configure those old devices. Essentially the
    byteblaster drives the same signals as a config device like an EPC1.
    The byteblaster is not connected to the JTAG header, instead it is connected
    to a header with connections to the serial config lines (DCLK, DATA, OE,
    nCS, etc). The pinout is in the byteblaster docs. The same header is
    used to program the serial eeprom in-circuit, although there may have
    been quirks for the old EPC2-era devices. I didn't include on on my board
    at all.
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