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JK flip flop

Discussion in 'Electronics Homework Help' started by Daniel Hammond, Mar 14, 2016.

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  1. Daniel Hammond

    Daniel Hammond

    3
    0
    Jan 18, 2016
    I am trying to simulate a JK flip flop in yenka. I have simulated an RS flip flop which gave the correct outputs as per the truth table when modifying it to a jk flip flop it does not give the correct outputs, why is this?
     

    Attached Files:

  2. Harald Kapp

    Harald Kapp Moderator Moderator

    10,327
    2,243
    Nov 17, 2011
    You have switches to put 5V (logic high) on the gates' inputs, but not for 0V (logic low). I don't know yenka, but could this be the cause?
     
  3. Anon_LG

    Anon_LG

    453
    117
    Jun 24, 2014
    In yenka you are expected to include a "vdd" sign with one lead connected to a positive supply symbol and the other to a ground symbol. This will "power" all of your logic. No idea why this is a feature. You will find the necessary under "logic" if memory serves.

    Also, when working with logic in yenka, you should use the premade logic inputs. This simplifies greatly.
     
  4. Daniel Hammond

    Daniel Hammond

    3
    0
    Jan 18, 2016
    Thanks for the replies. I thought if the switch is open that would be logic low?

    I would normally use the pre made logic inputs but the question (this is for an assignment) asks to use switches for inputs and for the clock pulse. I have drawn the circuit using the premade logic inputs and a logic indicator instead of the led but it is still not giving the correct output (jpg attached), in this image j,k and clock are set to high the output is high-high but should be low-high or high-low? Thanks.
     

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      jkff.jpg
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