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JK & D flip-flop circuit, basic stuff - plz help

n3rollo

Nov 14, 2009
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Hi guys,

I need a quick advice about my assignment.
It is regarding a use of JK flip flop and D flip flops.

Regards.
 

cj_elec_tech

Oct 7, 2009
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Gee n3rollo, I'd be happy to help you if you had a 'legitimate' and puzzling problem to address, but seriously YOU need to work these questions out; after all they are being asked to get YOU to learn digital electronics.
Why would you expect anyone here to do your homework for you?
 

n3rollo

Nov 14, 2009
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Hey cj_elec_tech, thanks for your reply. I agree that solving it for me is pointless. I would rather get a reasonable advice so it direct me how to start. If you have one for me I'd be ecstatic.
 

cj_elec_tech

Oct 7, 2009
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Well, I tackle these sort of problems by writing the truth table (TT) for what needs to be achieved, then look at the TTs for the gates etc that are available and deduce how to make those 'fit' into the main TT - in my head, it sorta works like a crossword puzzle.
Another way to tackle the problem is to write the logic equation(s) for what needs to be achieved and see if the 'structure' of the equations relates back to the gates available for use, thus enabling One to construct what is required - personally, I never could do it well this way, it's too much like Math, which I'm hopeless at.

Does the way that the questions are being asked cause you confusion?
Always keep it in mind that ANY logic problem is only built up from basic building blocks - just like bricks in a house - put them together the right way and you can make anything!
"Give me a few bucket-loads of NAND gates and I could build a you a PC" - that's what I've frequently said to others and, whilst it might sound a little trite, it's basically true. The trick is not to get overwhelmed with the complexity of the problem, always tackle it one bit at a time.
(or one Byte at a time, or one Nibble at a time ;) <snigger>, sorry couldn't resist that! :) )

Hope this rant helps you, let us know how you go.

CJ
 

n3rollo

Nov 14, 2009
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I've got the truth table (question1) but deducing what gates fit into it is still a trial and error method for me.
 

cj_elec_tech

Oct 7, 2009
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Q1:
Break the problem into smaller bricks; Clearly there are 2 parts to this question - 2 output conditions are explicitly stated:

a) "if M=1, the flip-flop negates the current state"
- 'flip-flop' in this context refers to the CMN flip flop (FF) 'block' (or 'black box', if you like to think of it this way) that you are creating.
- no 'next state' has been stated, so the output change is asynchronous, thus the CMNFF output MUST come from the output of a GATE.
- So what Gate's output is the inverse (negate) of one of it's inputs when the other input (M) = 1?
- Check the TT for each logic gate: ANSWER = NAND.

So:
- the Q for CMNFF must be the output of a NAND gate
- the M input must be one of the NANDs inputs

b) "if M=0 the next state is equal to the value of N"
- a "next state" is stated, so you'll be using a FF to make the o/p change synchronously: Obviously this will be a JKFF 'cause that's the only one you're given.
- the o/p of the JKFF must go to the other NAND input from part a) to ensure part a)'s output criteria is still met - BUT (always!) double check the TT for NAND to ensure that it is 'transparent' (output = other input) when M = 0 ........ DOH! it's not! It's always a 1! Therefore NAND was wrong! SO lets go back a step....

to be continued...
 
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cj_elec_tech

Oct 7, 2009
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What other Gate negates it's output if one input is high, BUT not if that input is low?
ANSWER = XOR!
Damn, I should have seen that when I first looked at the TTs in part a), but I didn't write the xor TT on my piece of scrap paper 'cause I was lazy - maybe YOU saw that and got confused when I selected NAND???
Anyway, the lesson to learn from my error was that I RECHECKED the NAND TT when I started part b) and found my error - so (now write this down and put it in a frame and hang it on the wall)
ALWAYS CHECK ALL POSSIBLE STATES WHEN DESIGNING LOGIC!!!
trust me; get into that habit NOW and you'll save yourself a whole heap of anguish when you design some vastly complicated State Machine with multi-triggering asynchronous inputs and a partridge in a Pear Tree!

Thus the correct answer for a) was XOR gate.
(phew, got that sorted, back to part b) now ;) )
 

cj_elec_tech

Oct 7, 2009
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b) "if M=0 the next state is equal to the value of N"
- a "next state" is stated, so you'll be using a FF to make the o/p change synchronously: Obviously this will be a JKFF 'cause that's the only one you're given.
- the o/p of the JKFF must go to the other XOR input from part a) to ensure part a)'s output criteria is still met - check it.... it does ;)
- the TT for "..next state is equal to the value of N" describes the TT of a DFF, so how do you make a JKFF look like a DFF?
OK from recollection you just connect the JK inputs together (and I should check that but I'll let you do it 'cause I'm tired of typing/thinking :p and I'm lazy and don't want to look it up 'cause it's over 20 years since I last used a JKFF explicitly and I've actually forgotten the TT...:rolleyes:)

So N = JK inputs, the JKQ = one i/p of XOR, other i/p of XOR = M and MNFFQ = XOR o/p

I think... ;)
 
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cj_elec_tech

Oct 7, 2009
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Can you see how I broke the problem down into little tiny bricks and CHECKED the function of each as I constructed my bigger brick (block)?

Also note how it's actually EASIER to start from the output and work backwards to the input - in fact it was quite obvious to me (initially) that we needed an 'or-type' gate for part a) when I saw there were 2 output requirements: requirement a) OR requirement b), 'geddit?
(a NAND IS an or-type gate, just one with negative-logic inputs, so I was happy to use it at the time....)
 
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cj_elec_tech

Oct 7, 2009
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Question 2,a) is straight-forward, just write the TT

Break Q2b into halves (well 'sorta) and tackle the easy bit first:
1) 2 bits => 2 instances of the bimem block (in parallel, as it were - think 'columns'), so the individual Ss and Cs are simply connected together.

next half:
2) 2 addresses means 2 instances of the bimem block (sorta in series, well actually it's parallel - think 'rows') with one or the other's output selected (which is the address)

Sanity check:
2 instances of 2 bits (2 times 2) = 4 bimem blocks, which he tells you in the question! (but I'm trying to show you HOW to break the problem into tiny bricks, remember?)
You could draw the blocks as a 'matrix' of 2 by 2 (which is why I said think rows and columns) and this is exactly what a memory block IS - a matrix of memory elements (bits); hence the block you are given was called 'bi(t)mem'! See, you're told what it does by it's name! The problem's not that hard after all...:rolleyes:
 
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cj_elec_tech

Oct 7, 2009
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2,b),2) continued...
Now you 'just' need to work out how to connect the Ss, Cs and Q's 'together' to select which ROW gets selected for which address - it's a good thing you wrote bimem's TT in 2,a) earlier huh? - you know HOW bimem works already!:rolleyes:
And 'coincidentally', you've already designed a circuit that used a 'select which' in question 1 earlier, huh?:rolleyes: (my 'sorta series' statement above should make sense when you sort the design out)......

I'll leave the rest to you - I need to go and do some work after all that typing!
;)
Please let us know how you go.

CJ
 
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n3rollo

Nov 14, 2009
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cj_elec_tech, thank you for your time, I worked through your recipe and a lot of it made sense for me, however your answers were not exactly as our tutor expected us to produce. Thanks again for your help.
 

neon

Oct 21, 2006
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A 'd' flip flop will follow data with clock trnsistion . A jk has a master and a slave flip flopit cannot follow a clock must set the slave first then transfer good enough for you?
 

neon

Oct 21, 2006
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The only differnce from D nd JK i that d will toggle with data with clock while JK will toggle with clock as a master and a slave flip-flop also with clock.
 
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