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JFET Transistor Biasing?

Discussion in 'General Electronics Discussion' started by commathe, Oct 8, 2013.

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  1. commathe


    Oct 8, 2013
    Hey everyone,

    I have been running some simulations of JFETs in order to study a bit about how to bias JFETs properly and also to teach myself along the way. I'm having problem with some of my calculations though. I am currently able to accurately calculate the operating point of a simple JFET circuit so long as it only has a source resistor. However, I've noticed that as soon as the drain resistor gets large enough to limit the current to be lower than the expected current draw for some source resitor and Idss value, then the operating point of the transistor becomes elusive and strange to me and I'm unable to calculate it. I feel that it has something to do with changes in drain-source voltage drop (maybe gate-source too?) but I can't figure out exactly how to calculate it accurately.

    Similarly, I am confused as to how to bias a JFET well enough as to basically negate the differences between individual components - similar to how you can by using a voltage divider bias network for a BJT.

  2. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    Nov 28, 2011
    Hi commathe and welcome to the Electronics Point forums :)

    The source voltage in a JFET amplifier stage is created by current flowing through the drain resistor, through the drain-source path within the JFET, and through the source resistor. The JFET controls the amount of current that flows through it so that the source voltage is correct to give the correct amount of gate-source negative bias. If you make the drain resistor too high, the JFET cannot provide enough current to provide the required source voltage - the drain voltage drops so far (due to voltage drop across the drain resistor because of the current the JFET is trying to pass) that there isn't enough voltage left to provide the required amount of source voltage. Perhaps that is what's happening with your circuit?

    That's a good question about biasing a JFET to reduce the effect of component variations. It's more difficult with a JFET because the gate-source voltage for a given drain current is not as well-controlled as the base-emitter voltage for a BJT. Offhand I can't think of any simple tricks that would help. It should be possible to add DC feedback to keep the operating point within a limited range, but I can't see how to do that without adding at least one active component. Try a Google search!
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