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It's Official... PSpice Schematics v10.3!

Discussion in 'Electronic Design' started by Jim Thompson, Nov 15, 2004.

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  1. Jim Thompson

    Jim Thompson Guest


    Newsgroups: alt.binaries.schematics.electronic
    Subject: PSpice Schematics v10.3 Is Official! -
    Message-ID: <>

    ...Jim Thompson
  2. Ken Smith

    Ken Smith Guest

    My ISP doesn't think there is such a group and Deja doesn't archive the
    binary groups. How do I view that group?
  3. Jim Thompson

    Jim Thompson Guest

    Change ISPs ?:)

    It was just a screen shot of v10.3 showing markers and bias indicators
    still functioning.

    Only a big deal if you're in to PSpice Schematics as a front-end.

    ...Jim Thompson
  4. Chaos Master

    Chaos Master Guest

  5. Chaos Master

    Chaos Master Guest

  6. This has been in SuperSpice for quite some time. :) :) <grin>

    Melvin Stevens
  7. Jim Thompson

    Jim Thompson Guest


    Whoopy Doo!

    It's been in PSpice as long as I can remember. The problem was one of
    whether OrCAD/Cadence was going to continue its support, or whether a
    bunch of us would bail to another simulator.

    Please don't start about simulators that I consider to be toys... this
    is a documentation/how-I-earn-my-living issue.

    ...Jim Thompson
  8. Chaos Master

    Chaos Master Guest

  9. Ken Smith

    Ken Smith Guest

    For sim. I use LTSpice. For product schematics, I use Orcad for DOS. For
    me, Spice is mostly about checking my math.
  10. qrk

    qrk Guest

    Did they add anything new or is it still the same?

  11. PaulCsouls

    PaulCsouls Guest

    I heard rumors that Orcad for DOS was now freeware.

    Paul C
  12. Joel Kolstad

    Joel Kolstad Guest

    It must take you a long time to do worst case analysis (i.e., Monte Carlo
    simulation) by hand. :)
  13. Ian

    Ian Guest

  14. Jim Thompson

    Jim Thompson Guest

    Don't know yet. I was waiting for Schematics confirmation before I
    laid down my bucks.

    ...Jim Thompson
  15. Jim Thompson

    Jim Thompson Guest

    "Simulators" was a bad choice of words. The real issue is user
    interface... the schematic entry... then the post processing of data
    so that it's like looking at a lab scope.

    Schematic entry is where most fall apart, clumsy to use. Also many
    can't do an adequate job of hierarchical structures.

    I can draw a schematic using PSpice Schematics about as fast as I can
    with a pencil, which is why I swear by it so much... every motion is
    intuitive and natural.

    And it seems the more expensive they are the klutzier they get ;-)

    ...Jim Thompson
  16. Oh dear...I expected more you. Why on earth do you want the output to
    look like a real scope? This is the thing that makes it for the kiddies,
    like the play bench electronic workshop. Secondly, PSpice doesn't do
    that anyway. Its graphing is *not* a real time scope, so you seem a bit
    confused in your old age.
    SuperSpice has a brilliant GUI.
    In what way?
    As is SS. The reality is, Schematics is a bit long in the tooth. It
    misses quite a lot of features, although I agree, itd better that
    anything else out there, apart from SS that is.

    Kevin Aylward
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
  17. Joel,
    There's been some discussion on how to do Monte Carlo on the LTspice
    users' group,

  18. Ken Smith

    Ken Smith Guest

    But that isn't "worst case". The real worst case is that all the parts
    are at the worst extreme that the maker allows to be shipped to the
    customer they like the least. ie: the parts I will actually get in

    It takes surprising little time to do a real worst case check on a
    circuit. In a good design there is always a safety margin so all you have
    to do is prove that there is still some margin not the exact amount it
    will be.

    Spread sheets calculate fairly quickly even under Windoz.
  19. Joel Kolstad

    Joel Kolstad Guest

    Fair enough, but I think that Monte Carlo analysis (assuming you set
    realistic tolerances on each component's parameters) is representative of
    what happens in the real world... although, OK, maybe if you're not the
    'least liked' guy on the manufacturer's list!

    Many simulators have a 'Yield' option that's effectively Monte Carlo
    analysis where they also let you set guidelines for what a 'passing' or
    'failing' circuit response is and then collect statistics about your yield.
    Although obviously it would be nice if you could design circuits that always
    had a 100% yield, this tends to become increasingly difficult as you
    starting doing higher and higher frequency design and they are so many
    variables (such as the relative premeability of your PCB's substrate) that
    are difficult or merely expensive to precisely constrain. For some designs,
    it's cheaper overall to accept a lower yielder with 'looser' parts than
    require tighter tolerance components.

    I guess my point here is that while I'd readily admit that the average
    design out there probably could obtain a higher yield with no significant
    change in cost, there are also times when it's entirely reasonable to accept
    a lower yield just so that you can ship the @#$%@# product and get on with
    life. I've heard that the IC yields on high-end 3D graphics chips are
    abyssmal -- around 10% -- yet clearly there's a demand for them and it'd be
    absurd to suggest that they simply shouldn't be manufactured unless the
    yield could be increased.

    BTW, I suspect that if you simulate any of those chips with the absolute
    worst case tolerances on all the components the yield drops to 0%.

  20. Yes, this is one definition of WC, the one I use, and of course, SS does
    this automaticaly with a couple of button presses in the GUI.

    The other definition is when components have been adjusted to give the
    max/min voltages and currents, which is not the same, but you hope they
    If its done in a simulator, indeed. Doing it by hand is essentially,
    impossible. You cant even get a closed form solution for a general 1
    transister circuit, let alone one with 50 or 1000 of the buggers.
    Well, absolute proof is not possible. A WC may be 3 or 6 standard
    deviations from the norm. There is always a probability of violations of
    these limits. Not everything is tested and culled to its stated limit.

    Kevin Aylward
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
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