Not necessarily. I know what they did on one part years ago, but I
haven't looked recently -- maybe they have figured out a clean way to do
this that involves an oscillator running at 256MHz. It'd certainly solve
a bunch of problems with variable time delays, even as it introduced a
bunch of other ones.
Well, as I pointed to before, take a look at Figure 19-2 in
the Family User's Guide, found following from here:
http://www.ti.com/product/msp430f5172&DCMP=msp430&HQS=430timer
It is behaviorally diagrammed as a fast clock generator
followed by your basic /1 /2 /4 /8 divider. It picks off of
the IDEX divider against the regular clock sources, so on
that level it looks like a normal multiplier. It includes an
"in-lock" bit, TDHLKIFG, to inform you when lock is achieved.
It also runs completely free. No lock, no care about another
oscillator, at all. So all that makes me think they actually
have a fast internal DCO of some kind, but where it can
optionally be locked to a lower speed crystal source.
Some words may relate to what you were saying, Tim. I see
this:
In regulated mode, the high-resolution generator
produces 8 or 16 equidistant events per timer
input clock cycle. Regulation is enabled by setting
the high-resolution calibration enable bit TDHREGEN.
The high-resolution generator tracks changes of the
timer input clock after locking to the timer input
clock frequency. Locking is indicated by setting the
lock interrupt flag TDHLKIFG. As long as the high-
resolution generator is not locked, the interrupt
flag TDHUNLKIFG is set.
If the timer input clock is out of the frequency
range of the high-resolution generator, then the
fail-high interrupt flag (TDHFHIFG) or the fail-
low interrupt flag (TDHFLIFG) is set.
If the TDHREGEN bit is cleared, the continuous
regulation is stopped and the high-resolution
frequency enters free-running mode. The latest
settings are kept.
There is no datasheet yet and so I can't look at related
specs that might help elucidate any better. I assumed that
they folded in Nat Semi technology (they are doing this with
their work on FRAM, too) to reach 256MHz in their process.
It's a little odd on the MSP430, as it goes upstream of their
"extremely low power" selling point (valid and well-made.) If
they were doing this and keeping most of the high clock rate
stuff tightly contained in small region of the die, perhaps
it would still be 'congruent.' But they use it to drive an
entire timer counter and this also means fast compare logic,
as well. So it starts to look like more die space is involved
than less and I have to imagine current draw will be
unusually high then.
Still, it is another selling point corner, I suppose.
Jon