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Is this a PLL?

Discussion in 'Electronic Design' started by Tim Shoppa, Aug 10, 2005.

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  1. Tim Shoppa

    Tim Shoppa Guest

    I've dealt with:

    1. "Regular" PLL's where there's a VCO and a phase detector and
    a loop filter and the frequency is slewed to phase-lock the VCO
    to a reference.

    But I also occasionally deal with:

    2. Clock-recovery circuits that don't really have a variable-frequency
    oscillator. There is a clock, but it's fixed frequency and
    typically runs 8x or 16x (or sometimes more) higher than the data
    rate. There's a shift register and a clock-pulse recovery
    subcircuit, and the the shift register has its phase adjusted
    +/- a clock or two to keep the data separator locked to the data.

    Is #2 a PLL? It is phase-locked, but doesn't really have a variable
    frequency that "remembers" the last time it was locked (in the
    absence of a data stream it ticks along solely
    according to the fixed-frequency clock without any adjustment).

    I have sometimes seen things like #2 called a "digital PLL" but
    my gut feeling is to call it a "data separator".

    And there's a third category:

    3. A digital PLL with a "numerically controlled oscillator", e.g.
    frequency really is being adjusted (not just phase), but it's
    all done with counters instead of a VCO.

    Maybe #3 is a true "digital PLL".

    Am I too picky about nomenclature?

    Tim.
     
  2. Tim Wescott

    Tim Wescott Guest

    I have seen #2 called a PLL -- I have even called #2 a PLL because I
    knew that calling it a "frequency locked loop" or a "automatic clock
    adjuster" would harvest me a bunch of confusion, and, when explained, an
    exasperated "well that's just a PLL!".

    I certainly consider #3 to be a PLL.
     
  3. Jim Thompson

    Jim Thompson Guest

    So it's phase AND frequency locked.
    I still call those PLL's or phase jerkers ;-) Very handy for systems
    with missing data transitions that ordinary PFD's throw up over.
    Picky is as picky does ;-)

    ...Jim Thompson
     
  4. Tim Shoppa

    Tim Shoppa Guest

    I still call those [...] phase jerkers ;-)

    I like it. Succinct.

    Tim.
     
  5. Jim Thompson

    Jim Thompson Guest

    I've used that scheme since the late '70's to lock to such
    intermittent data as, for example, floppies.

    It will also lock to video that, for some reason, is missing some sync
    ;-)

    ...Jim Thompson
     
  6. Tim Shoppa

    Tim Shoppa Guest

    I've used that scheme since the late '70's to lock
    Did you design the data separator in the WD floppy chip application
    notes? It's a phase jerker from around that time frame... (and sure
    beat the RC one-shots in the competition!)

    Tim.
     
  7. Jim Thompson

    Jim Thompson Guest

    I designed the one for the GenRad PSP portable tester. I used to demo
    it by swinging the case around my head in all kinds of gyrations while
    it merrily kept on reading without error. It would withstand a huge
    speed variation without a problem.

    I'll post it when I find a copy.

    Found it! Watch for it on A.B.S.E

    ...Jim Thompson
     
  8. Jim Thompson

    Jim Thompson Guest

    See...

    Newsgroups: alt.binaries.schematics.electronic
    Subject: Phase "Jerker" from S.E.D - FloppyClockRestore.pdf
    Message-ID: <>

    ...Jim Thompson
     
  9. No, it makes a big difference in detecting data streams in noise.
    They are all PLL, with 1 being the best, then 3, and 2 is dependent upon F
    at transmit to be right on receive F, a weaker design.
    #1 may work in 5 dB SNR, #2 may require 20 dB SNR to work.
    Phase and frequency are not completely separable.
     
  10. Mike

    Mike Guest

    Quite possibly.

    Delaying a clock by dQ every M cycles is the same as decreasing the
    frequency by a factor of M/(M+dQ). You can accomplish the same goal by
    dividing a clock (possibly with a different starting frequency) by N+1
    instead of N.

    You haven't provided any information about the rest of the system in #2 and
    #3, so it's not clear to me whether or not they're equivalent, but they
    certainly could be. By the same token, whether or not the output in #2 stops
    incrementing without data is a function of the loop architecture.

    -- Mike --
     
  11. Jim Thompson

    Jim Thompson Guest

    Working SNR depends on *type* of phase detector, band-limiting, etc.

    ...Jim Thompson
     
  12. Guest

    night soil dalits skrev:
    2 works just fine for the majority of uarts and that's with
    transmit-recieve
    frequency differences in percent..

    with a nco clocked fast enough compared to the output 3 could be just
    as good as 1, and could probably be made even better because you could
    add a much more intelligent detector/feedback algorithm...

    -Lasse
     
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