Inverter performance

[lerameur]

Hello,

I made two inverter circuit:
http://www3.sympatico.ca/captoro/inverter.gif
My goal is to have about 33-33v in the output to drive some mosfets.
I am not about which circuit is more stable, the one with OP amp or
the one below with just the Mosfets.
The problem with the CMOS inverter is that I need three steps instead
of two. Mainly because the gate voltage is not high enough, but I
cannot put it higher then 12v.
As for the OPAMP circuit, I can use the MC34071 OPAMP which has a max
of 44v supply.
Which circuit should I use, or any modification to be done ?

thanks

K

 

[lerameur]

They both have problems.

The opamp circuit will swing the gate drives slowly, because
the opamps have a slew rate limit on their outputs of a
fraction of a volt per microsecond.  Also, the reference
voltage for both opamps should be about mid way between the
swing extremes of the signal input.

In the triple CMOS inverter version, you should check the
current through the first stage.  They are a huge load
across the 30 volt supply.

Hi,

Ok, I modified the circuits, let me know if this is what you meant.
So the better circuit will be the CMOS gate.

k

 

[lerameur]

Hi,

Ok, I modified the circuits, let me know if this is what you meant.
So the better circuit will be the CMOS gate.

k

Here is the link:
http://www3.sympatico.ca/captoro/inverter2.gif


k

 

[lerameur]

I see not differences at the original URL.

And I did not say one was better than the other.
I said they are both flawed.

If you replace the opamps with comparators and add some gate
drive current boosters (complementary emitter followers,
perhaps), I think that might beat both these designs, but
then, I have not seen your changes.

The second link I posted above

K

 

[lerameur]

That is what I had in mind for the opamp version, but adding
the resistors to the CMOS version, essentially eliminates
the function of the P-channel devices.  You might as well
eliminate them.  And, of course, you no longer have any pull
up capability for the outputs, and the pull up delay for the
first output also delays the pull down of the second output.

What is missing is level shifting for the first stage, that
turns off the P-channel device when the N-channel s on and
vice versa.  If you get that right, the other stages are not
so bad as simple inverters (with maybe a little source
resistance in all transistors to limit the shoot through
current during switching).  I think the next to last stage
should also be built as two stages in parallel, one to drive
the external inverter and one to drive the other driver, to
keep the gate load on the first one from delaying switching
of the second one.

John,

I put the OPAMP in parallel, the problem is what you mentioned
earlier about the slow slew rate.
Also about the second circuit, I understand about putting them in
parallel , but I am not sure what you mean by " level shifting for
the first stage"

k