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Interfacing to a parallel port

Discussion in 'Electronic Basics' started by Tom Yaney, Jan 14, 2004.

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  1. Tom Yaney

    Tom Yaney Guest

    Hi all--

    The thread below appeared several years ago in sci.electronics.basics.
    I have a similiar problem interfacing to a parallel port, and I like
    Steve's suggestion of using a toggling output to signal an "IOGOOD"
    condition to enable tri-state outputs. The trouble is, I have no idea
    how to implement a circuit that detects a toggling signal. Steve
    seemed to imply that it was fairly easy to do though. Any ideas?
    Thanks for your help!


    We design embedded circuitry - we don't really just interface relays
    parallel ports - but the principles are the same. I'm not going to
    draw out a circuit for you, but I'll give you enough info so you can
    do it yourself once you get the datasheets

    The best method (IMHO, and I should bloody know ;-) is to take
    the signals through a 3-state buffer, latch, or register, and run the
    3 state enable from your delay circuit. If you're stuck selecting a
    chip, try a 74LS245, just wire the direction pin so that the buffers
    "point" the right way. The only other pins are inputs, outputs,
    power, gnd and 3 state enable, so you should be right drawing
    out this bit of circuitry.

    You *could* enable your buffers from a signal that goes active
    a little while after power up. For instance an ic555 ;-)
    The high pulse keeps the buffers off after power up, when it
    goes low, the buffers are enabled and the signals get through.
    You will find a monostable design for a 555 timer in its data
    sheet - pick the resistor/capacitor values to give you the
    time delay you need, feed the 555 output to the 3 state enable.
    Remember to trigger the 555 so it goes active on power up.

    Depending on what you are running, you use the 3-state
    condition to keep the signals off. If you are running a
    transistor, LED, or such like, it happens by default. If you
    are running a CMOS or TTL circuit, you will need a pullup
    or pulldown resistor (if you are stuck for a value, try 10k)
    to bias the output to its inactive state when it is 3 stated.

    Once you understand what I am describing here - there is
    a nifty enhancement you can make. You find a signal somewhere,
    such as a spare output, and toggle this output continuously in
    software. In hardware you detect this toggling, and use it
    to enable your 3-stated outputs. As long as this extra output
    is toggling, your 3 stated outputs are enabled. If the your
    extra output stops toggling, your main outputs turn off.
    Its a nifty protection mechanism for if your computer crashes,
    or your software isn't run, or any other reason - it stops the
    outputs being turned on when there is no software there
    to control them. Basically its a "dead mans handle"
    I use it quite a bit in embedded electronics and call it

  2. Si Ballenger

    Si Ballenger Guest

    I can't speak to the 3-state toggling, but you might use a
    sequence to control the parallel port pins that is imune to the
    on/off cycling of the pins during the computer boot. I've got a
    link below where I've got some chips that might get around the
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