Instruction And Data memory

Can someone tell me what is the difference between Instruction and data
memory

 

I assume you are looking at a processor that has support for such
things (or a system that has such a processor or MMU).

The difference is that instruction memory is exactly that: memory
referenced during an instruction fetch (the newer processors
discriminate between the various bus cycle types) and data memory is
for just that: data.

There are a number of reasons for this, and they have separate origins.

Access level control. In a processor that supports the notion of
privilege levels (the vast majority of 32 bits devices and up),
I-memory can be marked as read-only at user level (so a program may not
modify it's own code), and writeable only by supervisory level(s),
usually an OS function - for instance, the OS has to write that memory
to load the program in the first place.

Data memory, on the other hand, is expected to be modified by a
program, so the access to it is freely given to it's parent process
(although other processes may not be given access - this subject has
books written about it).

Cache efficiency. Most processors have a D-cache and an I-cache. A
cache holds recent instructions and data (and I am not going to get
into just how recent or what type of algorithm - there are tomes out
there on that).

If a cache has to be refilled, it's primarily for one of two reasons
(there can be others): either the data required is not in the cache (a
D-cache issue) or a branch/jump just invalidated the cached
instructions, requiring an I-cache refill. As these two things do not
happen synchronously (they do happen at the same time occasionally, but
they are not statistically synchronous), separating the two makes sense
to optimise the cache system.

That's a very broad brush overview of a complex subject, leaving out a
huge amount of background, but it should give you the flavour of the
idea behind it.

Cheers

PeteS

 

Some processors actually have physically separate hardware for program
and data memory. It's a way to double memory bandwidth: the next
instruction is fetched while the current instruction is executing. It
can also simplify CPU hardware; some early computers worked this way.
Some embedded microcontrollers have a small data RAM plus some k-bytes
of read-only EEPROM program memory, which is not data-addressable.

 

[snip explanation]

I'd make explicit that there is no technical difference between
instruction memory and data memory, in case that was what the
intent of the OP's question. They are the same kind of RAM since
drum storage was scrapped. Any differences in behavior are by design,
not by the nature of one or the other.

Instruction memory runs with von Neumann's blessings, data memory
doesn't.

Anno

 

Not necessarily. Instruction memory can be quite different than data
memory in a Harvard Architecture processor.

Not on purpose anyway. ;-)

 

Instruction memory is the memory that instructions are fetched from,
and data memory is the memory where the data is written to and read from.
;-P

Cheers!
Rich

 

[instruction memory vs. data memory]

Ah, okay...

It is a strange, if off-topic, observation that von Neumann made modern
computing possible by bridging the gap between instructions and data,
but modern computing does everything to make them as clearly distinct
as possible. It must, to stay sane (Lisp-programmers excluded

Anno

 

Yes, indeed. AMD introduced the No-Execute bit in the page table on
x86 processors to further segregate data and memory.

Sure, Lisp programmers are excluded from those trying to stay sane.
;-)

 

It had nothing to do with modern computing- both architectures were
proposals for the most efficient implementation of a relay logic
computing machine to be used to generate Navy gun tables during WWII.
Von Neumann won. Interesting that it became Von Neumann vs Harvard
instead of Princeton vs Harvard. The integrated circuit technology made
"modern computing" *possible*- before that they were impossibly large
and power hungry behemoths.

 

I think the reference was to the Von Neumann processors now trying to
isolate instructions and data as much as possible. Seperate I and D
caches certtainly suggest this, as do Icaches without write ports. The NX
bit in the page table is another move along this line.

I've heard both.

....and now we have impossibly small and power hungry behemoths. ;-)

 

keith wrote:

[...]

It could be worse. Here's what a Pentium IV might look like with tubes:

http://www.ominous-valve.com/vtsc.html

Mike Monett

 

LOL- the modern architectures are so far removed from anything envisaged
in the 1940's- it makes no sense to even use the terminology of
Harvard/Princeton. Von Neumann was working on a multitude of real world
problems of national strategic importance at the time and his work was
heavily influenced by the reality of low risk and proven hardware
availability and schedule.

Right- well the molecular computing is going to put most of the
electronics engineering as we now know it out of business in short order.

 

Not at all. There is a rather big difference between the two. A modern
x86 doesn't do well with self-modifying code, but it can. An 8051 OTOH.
The first is clearly Princeton and the latter clearly Harvard.

....for large values of "short".

 

ROFLMAO!

Thanks!
Rich

 

It's a bunch of academic bs...no one pays attention to it...

Positively instantaneous compared to anything done today in this
pathetically over bureaucratized cesspool world full of incompetents...

 

My two cents: I dunno where to clip, so I'll quote the whole thing
down to my comment.

Most DSP processors are Harvard - while there are often some
special instructions to read and write program memory with data, the
usual operation is to be fetching program memory and reading/writing
data memory simultaneously through two separate buses.
Though modern general-purpose processors such as Pentium have
separate caches for program and data access, they're both tied to the
same main memory that can only read or write one word at a time. This
is easily recognizable as a Von Neuman architecture, distinct from
DSPs' Harvard architechture.

 

Because you're ignorant, doesn't mean everyone else is.

What a paranoid (as silly) attitude, though no surprise coming from
you, Fred. I'll never see it.

 

The PIC is a better example for Harvard. The 8051 uses the same bus but a
different command signal. The PIC has a bus just for instuctions.

 

Architecturally the memories are completely separate (one cannot
execute data memory and cannot write instruction memory). Of course
one can always connect the two externally, but that's altering the
architecture. If the 8051 uses internal instruction memory, they are
physically separate as well.

 

IIRC, I once scoured the PIC datasheet - _A_ PIC datasheet - to see how
hard a lookup table would be. Turns out it's a SOB.

Thanks,
Rich