Input stage mess

[Fred Bartoli]

I've done things like that and have a couple of suggestions:
note the points A and B.



(1)
If you add a switch and to switch in a lower resistance between A and B,
you can get the circuit settled more quickly.

(2)
If you add a series RC from A to B you can add a zero to the bias point
servo. You can use this to get rid of peaking at the gain cross over
point.

Ken,
the pb here, as noted by Phil, isn't introducing a zero somewhere, which I
stupidly forgot in the ascii art, and finding where to insert it. It's
mainly the 1G resistor that limits the slewing rate to about 15mV/s which
imposes impractical settling times if left as is. So I also have to switch
some "low" value resistor in parallel to the 1G to allow fast settling
times, then once settled, switch in the rigth time constants to obtain the
full specs (and obviously preserve stability). This was purposely omitted in
the ascii art for clarity.

One thing to take care of is the switch leakages (shot noise in the
protection diodes), hopefully not more than 1 or 2 JFETs gate leakage (so
under 4pA) in order to preserve the low low frequency noise.

 

[Mark]

ok, so this is not for an audio mic pre....so ultra low distortion is
not a requirement

so what you need is a 50 Ohm amplifer with BW from say 10kHz to 1 MHz
with a low noise figure?? They make amplifiers with < 1 dB noise
figure at 1 GHz these days.

So why have the big feedback loop which is creating your instability
problem and cannot help noise figure?

How about a J310 Nch JFET in common gate, really simple and low noise

Also I would think that a passive LC filter would be VERY effective at
reducing the noise out of a power supply in the 1 MHz region...

and if it is a switching supply, I cannot imagine that the random noise
is a bigger problem compared to the switching freq..

if it is a linear PSU , a few sections of passive filter should take
the random noise down to the thermal noise floor..

what am I missing?

Mark

 

[Frank Miles]

Fred Bartoli

[snip]

Well, I've finally got doing that low noise preamp: the target is
200pV/rtHz, bandwidth from 0.1Hz (with provision for 1/f noise) to

1MHz.

[snip]

85mA 85mA
to to
125mA 125mA

V V
| |
+------------------------+--------.
| | | |
.--+ .--+-----+--------. | |
| .-.R3 | .-.R4 | /| | | |\ |
---| | ---| | >| /-|-' '-|-\ |<
---| | ---| | |-< | | >-|
| '-' | '-' /| \+|--+--|+/ |\
'--+ '--+ | \| | |/ |
| | | 2 V |
clamp --. | .-------------------' |
| | | | | | ___
| | | | | .---------------------|___|-.
10u | J1 |-+ | +-|J2 | | | R2 |
|| | | | | | | ___ | |\ |
in -+--||--+--->|-+ | +-|<-------+-|___|-. | .----|+\ |
| || | | | | |5mA R1 | 5mA| | | >-+-out
.-. .-. '---+---' | | GND | | GND .-|-/ |
| | | | | | V V | | |/ |
| | | | | .-----------------------. | |
1M'-' '-'1G | | Precision |--+--||--+
| | V | current mirror | .-.
GND | 160mA '-----------------------' | |
| to /| | |
| 240mA /+|-GND'-'
'------------------------------------------+-< | |
| \-|-+---'
| \| |
'-||---'

[snip]

Yup. From the whole bunch of pb I could list I'm pretty safe to say that
this is probably the limit of what's doable at room temperature.

I don't know if you can meet the noise specs by going down this pathway,
but if the series RC shunting the input adds too much noise, I think you're
going to have to bootstrap your input circuit to get rid of the negative RC
Zin. This will have to operate at high speed -- not at the slow speed of
the feedback loop. Of course there are limits to this approach as well, but
with the right topology you may be able to use a pure capacitance between J1's
gate and an appropriate virtual ground input node to provide a high frequency
boost to J1's source. This has been done, for example, in a few oscilloscope
vertical inputs to provide a wider-band input while reducing the dribble-up
behavior of real follower circuits which have capacitive loading.

Hmmm, now that sounds interesting. That really is a clever trick, if I
understood correctly what you meant.
Do you have any specific scope reference or schematics to look at?

The first place I saw this was in an early FET-input oscilloscope probe.
Unfortunately I can't recall the model. The idea is pretty simple, really:

|
|--+
|
in ------------->|--+
| |
| |------ out
| c |
_|_ \ |
___ \|______
| /|
| e </ |
| |
|__________|
| I

The capacitor is sized to steal enough HF energy from the input signal to
drive the next stage's input capacitance. Its inter-lead voltages never
experience any voltage change, so the device's capacitances never experience
any change in charge. Bootstrapping the drain is necessary, of course,
both to keep capacitive currents and thermals from wreaking their havoc.
Not shown, of course, is the input bias circuit. Since you're not interested
in dc this should make some aspects easier -- the bias can be servoed.
The current-source NPN can't be bootstrapped, to preserve the 'virtual ground'
seen by the low side of the input capacitor, but a souped-up variant could
be used in place of a simple/single NPN.

If you really don't need the impedance buffering, however, this may all be
pointless. You may have already tossed this, but perhaps you "only" need
to create a super-low-noise, stable sample-hold device, along with a somewhat
more traditional low-voltage-noise amplifier (with input protection). It
doesn't seem like you need the super-low Iin of the FET, do you? Of course,
such a sample-hold might be harder to build than the amplifier!

Good luck ... HTH...

-frank
--

 

[Fred Bartoli]

ok, so this is not for an audio mic pre....so ultra low distortion is
not a requirement

so what you need is a 50 Ohm amplifer with BW from say 10kHz to 1 MHz
with a low noise figure?? They make amplifiers with < 1 dB noise
figure at 1 GHz these days.

Yep, they make this. What I want is 200pV/rtHz (yes that's pV), which is a
2.5R noise resistance.
That translates to under 0.2dB noise figure for a 50R system.

So why have the big feedback loop which is creating your instability
problem and cannot help noise figure?

How about a J310 Nch JFET in common gate, really simple and low noise

Do the maths, its gfs is a pitiful 17mS typ. Plus the J310 has a huge low
frequency noise, spec'ed at 10nV/rtHz @ 100Hz, missing the target by a 50
factor. Not great and probably much much worse at 1Hz and 0.1Hz.

Also I would think that a passive LC filter would be VERY effective at
reducing the noise out of a power supply in the 1 MHz region...

No.

and if it is a switching supply, I cannot imagine that the random noise
is a bigger problem compared to the switching freq..

They are SMPS and are not a pb, but I won't give you all the details.

if it is a linear PSU , a few sections of passive filter should take
the random noise down to the thermal noise floor..

what am I missing?

The specs. by far, I'm afraid

Now you're welcomed to throw in a few components and submit your solution
here.
Here is the target:
- BW 0.1Hz - 1MHz
- noise floor 200pV/rtHz
- noise density at 0.1Hz not greater than 2nV/rtHz
- must cut the DC input voltage (up to +/- 15V)
- fast settling time (seconds)
- must also withstand 500mV input pulses and be able to characterise a
recovery to 200nV in 50uS
- must be floating
- should be user friendly

Oh, and you deliver it mid february.

 

[Jim Thompson]

On Wed, 30 Nov 2005 21:27:12 +0100, "Fred Bartoli"

[snip]

The specs. by far, I'm afraid

Now you're welcomed to throw in a few components and submit your solution
here.
Here is the target:
- BW 0.1Hz - 1MHz
- noise floor 200pV/rtHz
- noise density at 0.1Hz not greater than 2nV/rtHz
- must cut the DC input voltage (up to +/- 15V)
- fast settling time (seconds)
- must also withstand 500mV input pulses and be able to characterise a
recovery to 200nV in 50uS
- must be floating
- should be user friendly

Oh, and you deliver it mid february.

Looks like a cakewalk to me ;-)

...Jim Thompson

 

[Fred Bartoli]

On Wed, 30 Nov 2005 21:27:12 +0100, "Fred Bartoli"

[snip]

The specs. by far, I'm afraid

Now you're welcomed to throw in a few components and submit your solution
here.
Here is the target:
- BW 0.1Hz - 1MHz
- noise floor 200pV/rtHz
- noise density at 0.1Hz not greater than 2nV/rtHz
- must cut the DC input voltage (up to +/- 15V)
- fast settling time (seconds)
- must also withstand 500mV input pulses and be able to characterise a
recovery to 200nV in 50uS
- must be floating
- should be user friendly

Oh, and you deliver it mid february.

Looks like a cakewalk to me ;-)

Nah. You don't know how to design transistors by square meters

 

[Mark]

so you think you need an amplifer with a 0.2 dB noise figure to test a
power supply????

These kind of low noise figures are useful for satellite receivers
where the system noise is below the thermal noise floor of room
temperature since the antennas are pointed out into cold space.

Since the device you are measureing is at room temperature, it is not
logical to think that you need an amplifer with a noise figure better
then say 3 dB. An amplifer with a noise figure of 3 dB , when
connected to a room temperature source, (like yours) will deliver an
output signal S/N that is 3 dB worse compared to using a _perfect
noiseless_ amplifer. This should still be perfectly good for making a
measurment.

One of us does not understand your application,,, I hope it is me.

Have fun...

Mark

 

[Fred Bartoli]

so you think you need an amplifer with a 0.2 dB noise figure to test a
power supply????

These kind of low noise figures are useful for satellite receivers
where the system noise is below the thermal noise floor of room
temperature since the antennas are pointed out into cold space.

Since the device you are measureing is at room temperature, it is not
logical to think that you need an amplifer with a noise figure better
then say 3 dB. An amplifer with a noise figure of 3 dB , when
connected to a room temperature source, (like yours) will deliver an
output signal S/N that is 3 dB worse compared to using a _perfect
noiseless_ amplifer. This should still be perfectly good for making a
measurment.

One of us does not understand your application,,, I hope it is me.

I guess so.

Have fun...

Thanks.

 

[Fred Bartoli]

"Fred Bartoli"

Thanks Phil.
Comments inserted below.


"Phil Hobbs" <[email protected]> a écrit dans le
message de


I've measured some of the Jfets at under 2pA gate leakage under these
conditions, much better than the given specs and this is for a few boxes, so
that's OK for me. I was pleasently surprised because these are pretty big
transistors and this will simplify my already enough complicated life.

The 10uF are specified at 25000s minimum time constant, i.e. 2.5 gigaohm.
The input DC component is about 10V and I've again measured some samples
much better. Again I can select so it's OK too.

Have just tested a Philips (now Vishay-BC component) MKP378 2.2uF 250V.
They are amazingly good.
Under 20V bias, they show less than 1pA (probably 0.5pA) leakage.

That's more than 20000 Gohm isolation and an impressive 44.10^6 seconds
(>500days) time constant, for a 10^5 min specified.

I guess they'll be good enough

 

[Ken Smith]

stupidly forgot in the ascii art, and finding where to insert it. It's
mainly the 1G resistor that limits the slewing rate to about 15mV/s which
imposes impractical settling times if left as is.

You could make the op-amp swing to some outragous voltage like 100V to
speed things up a bit.

One thing to take care of is the switch leakages (shot noise in the
protection diodes), hopefully not more than 1 or 2 JFETs gate leakage (so
under 4pA) in order to preserve the low low frequency noise.

You may be able to make the protection diodes serve double purpose. If
their far ends are hooked to active circuits. you could drive them into
conduction to center the circuit.

 

[Ken Smith]

so you think you need an amplifer with a 0.2 dB noise figure to test a
power supply????

No, he needs an amplifier that has less noise voltage than the supply
does. The resistive component of the impedance at the output of the
supply is very low and hence the thermal noise floor is very low.

Try assuming the impedance of the system is 1 Ohm not the 50 Ohms you
normally think about.

 

[Fred Bartoli]

Fred Bartoli

[...]
stupidly forgot in the ascii art, and finding where to insert it. It's
mainly the 1G resistor that limits the slewing rate to about 15mV/s which
imposes impractical settling times if left as is.

You could make the op-amp swing to some outragous voltage like 100V to
speed things up a bit.

That'll reduce the settling time from 3 hours to about 20min. Much better
but the requirement is about 1 second (a few seconds at worst).

So will need 100kV with this scheme. Well probably not because when the arc
will trigger the 10u input cap will charge pretty fast

You may be able to make the protection diodes serve double purpose. If
their far ends are hooked to active circuits. you could drive them into
conduction to center the circuit.

Good idea. It'll require that I push the clamp level to 3 diodes drop
instead of 2 but that's probably OK.
Thanks.

 

[Mark]

No, he needs an amplifier that has less noise voltage than the supply
does. The resistive component of the impedance at the output of the
supply is very low and hence the thermal noise floor is very low.

Try assuming the impedance of the system is 1 Ohm not the 50 Ohms you
normally think about.

OK so the OP is trying to measure a very small voltage signal FROM A
VERY LOW SOURCE Z.

In which case he needs to look at amplifers with very low input noise
voltage but the input noise current is not critical. I think that
leads back to topologies that have a low input Z like common base or
common gate so that they are able to extract the most "power" from the
desired signal. A high Z input to an FET gate is not the correct
approach.

Mark

 

[Fred Bartoli]

OK so the OP is trying to measure a very small voltage signal FROM A
VERY LOW SOURCE Z.

In which case he needs to look at amplifers with very low input noise
voltage but the input noise current is not critical. I think that
leads back to topologies that have a low input Z like common base or
common gate so that they are able to extract the most "power" from the
desired signal. A high Z input to an FET gate is not the correct
approach.

You're still missing the point. The source is a power supply so I have to
block the DC component with... tadam! a cap which has a rising impedance at
low frequency, so the input current noise is of primary importance too. And
a fet input _is_ the correct approach.

If I had not that pb, the correct approach wouldn't be a discrete input
stage but toss 16 AD797 together and it's done. Unfortunately it isn't.

 

[Ken Smith]

In which case he needs to look at amplifers with very low input noise
voltage but the input noise current is not critical. I think that
leads back to topologies that have a low input Z like common base or
common gate

The input noise of a bipolar or FET appears as though it is a small
voltage source in series with the gate or base lead. Changing the
topology to gommon gate/base doesn't change the noise voltage. It just
lowers the power gain.

The OP is basically stuck. There is no way around the need to make the
input devices have a low noise voltage.

 

[Ken Smith]

If I had not that pb, the correct approach wouldn't be a discrete input
stage but toss 16 AD797 together and it's done. Unfortunately it isn't.

You could use a couple of hundred TL074 input stages.

BTW: You could use a common gate stage if you floated the whole thing at
the average input voltage. Sort of like this:


Input --+------ --------- To more stuff
! ! !
! -----
! ^
! !
-\/\/---+
1G !
--- 1F

 

[Phil Hobbs]

The OP is basically stuck. There is no way around the need to make the
input devices have a low noise voltage.

Except the correlation method, which only works for rms measurements.
OTOH, it can reach noise levels otherwise unattainable to
room-temperature circuitry.


Cheers,

Phil Hobbs

 

[Ken Smith]

Except the correlation method, which only works for rms measurements.
OTOH, it can reach noise levels otherwise unattainable to
room-temperature circuitry.

I assume in this case you mean:

(1)
Connect two amplifiers to the signal.

(2)
Multiply the outputs of said amplifiers.

(3)
Average the product and then SQRT() to get RMS.


This works ok but it does require longish averaging times if you want to
do a lot better than the amplifiers do on their own.

If you run each amplifier into an ADC and do a bit of math with them, You
can make a bandwidth filtered measurement to get the noise within some
band.

BTW: I've used this with an averaging time equal to one weekend.

 

[Mark]

going back to a higher level approach to the problem,,,,

if it is so hard to make this measurment, how is it that the
application circuit (that is being powered by this power supply) is
able to detect this noise so readily?

Mark

 

[Fred Bartoli]

going back to a higher level approach to the problem,,,,

if it is so hard to make this measurment, how is it that the
application circuit (that is being powered by this power supply) is
able to detect this noise so readily?

Eye seeing an whole region averages a lot of pixels + "contrast zooming" and
some other "small" things.

Having seen it, I can tell you it's absolutly obvious, even to the not
trained eyes, which are certainly not the final users.