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Input stage for VHF frequency counter in an FPGA?

Discussion in 'Electronic Design' started by [email protected], Feb 23, 2006.

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  1. Guest

    The other day I found myself needing a short gate time ~200 mhz
    frequency counter for an automated test, and since I had an FPGA board
    on hand I whipped one up quickly. Getting it reading and reporting to
    my computer was the easy part.

    Ah, the input stage....

    I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
    or a little more if it's high-Z. The output of the device under test
    has a transformer and then a series cap to create an unbalanced output.


    I did something ugly with a 3.3v cmos 7406 varient and a feedback
    resistor, which works well enough to get an accurate reading on one
    version of the device under test, but not on the other (both have been
    verified with real test equipment) It also tends to self-oscillate
    with no input...

    What would be the right way to do this using on hand parts, such as
    abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to
    use another gate with a feedback resistor and cap to ground in the hope
    of establishing the threshold level, and then using a transformer to
    swing another input above and below this. Most parts on hand are SMD -
    which means dead bug construction in SOIC scale under the maginifier -
    discourages extensive experimentation.

    Why do most abuse-of-logic RF applications seem to use NAND gates
    rather than inverters? From a digital perspective NAND gates are a
    universal element, but once you tie their inputs together, is there
    something to be gained from having two inputs in parallel?

    Is there a way to use a differential input configuration on an FPGA to
    input a balanced RF signal directly? Theoretically this should be an
    FPGA clock input... The device in use currently is an Altera Stratix
    II, but a Xilinx S3 kit is available.

    If ordering things, what would be a good default low supply voltage
    HF/VHF gain component to have on hand? I seem to recall lots of
    last-millenium ham designs using the MC1350P video IF amp, but what
    would make sense today?
     
  2. Does the FPGA have LVDS option inputs ?
    If it is new enough to have those, they are differential
    amplifiers, designed for current mode signals, and will work
    with thresholds << 1V.
    IIRC the LVDS spec has +100mV and -100mV levels.
    Normally, they need a common mode bias of just over 1V, and the
    better ones will also tolerate rail-rail drive (on ONE ip),
    but at reduced speed specs.
    -jg
     
  3. K7ITM

    K7ITM Guest

    For gain, have a look at MMICs. Minicircuits sell them in kits that
    give you a good range of performance. They're easy to use, and run on
    a single supply.

    I think the idea of using the LVDS inputs on the FPGA is a good one, if
    you can get that into the clock lines you need to use. Otherwise, you
    only need a little gain to get to levels you need for logic input. Do
    your clock input lines have a bit of hysterisis? Do they have high
    enough input impedance to be used with a step-up transformer? Can you
    reliably bias the transformer DC return to a point between the
    hysterisis trip-points. I suspect you can do a better job with your
    logic-gate amplifier, too. Or you could make a fancier input using one
    of the very fast comparators.

    Cheers,
    Tom
     
  4. John Adair

    John Adair Guest

    As Jim has said LVDS is a good way. Just watch the common mode input range.
    You can use a RF transformer to rebias the DC level to get arround any
    issues.

    Another way is to use a single ended standard like SSTL and DC bias the
    input to the reference voltage used for the SSTL. You do need to have access
    to Vref pins on the Spartan-3 to use this technique.

    We have support for LVDS and SSTL in our boards but I am not sure about the
    Spartan-3 starter kit.

    John Adair
    Enterpoint Ltd. - Home of Raggedstone1. The low Cost Spartan-3 Development
    Board.
    http://www.enterpoint.co.uk
     
  5. Hal Murray

    Hal Murray Guest

    7406 is open collector. Did you mean 7404?

    What size feedback resistor? What sort of oscillations?

    I've had reasonable luck with that sort of hacking. Not great.

    What's the output of your gate look like? Is it cleanly switching
    or struggling to switch at that speed?

    You might want to skip the external gate and use an inverter
    in the FPGA out to a feedback pin. That gets the feedback
    covering the input pin that you are really interested in.
     
  6. Beside that no frequency is mentioned, I'd have a
    look at line receivers.

    Rene
     
  7. Joseph2k

    Joseph2k Guest

    the only gain is some PWB layout simplifications and less wasted part
    sections.
    I am thinking on the order of a single transistor amplifier to go to logic
    levels, then characterize it for delay issues.
     
  8. Fred Bloggs

    Fred Bloggs Guest

  9. Fred Bloggs

    Fred Bloggs Guest

    Right- I've done this at the *old* TTL level with a single RF transistor
    CB stage at 200MHz; it's cheaper, simpler, and more compact to use a
    single chip broadband level translator.
     
  10. Just a partial reply... I think 7400 series should stop way below 200mHz,
    perhaps 50MHz?

    I would make a small diff amplifier, did something 40 years ago (yes 40!)
    with I think it was BFY90 transistors, then invert with 2 more and drive
    the LVDS input.

    -------------------------------- +5 or + 12
    | | |
    [ ] [ ] [ ] R4
    | |------------ __|__
    |-----|-------- | | |
    |/ \| | | |/>e < \|
    ---| NPN |---- | |----| |---
    in |\> e </ |bias2 | |\ PNP /| |
    |___| | | | |
    | ---------|-----|----
    | / | |
    ---| |---- |----------- LVDS +
    bias | \> | |----------- LVDS -
    | | |
    [ ] [ ] [ ]
    | | R5 | R6
    ---------------------------------------------- GND


    R4 could be a current source too, set it so it is guaranteed that
    the voltage across R5 and R6 (max i in one leg) cannot exceed FPGA
    max in.

    Gives you some input protection
    The 'bias voltages can be generated with diode drop.
    No time now to enter it in spice to get response.....
    You can use simple junction FETS for the first stage too.

    There are also nice chips, but transistors I have always in the box.
     
  11. Guest

    It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't
    tell) and it's self oscillating at 294 mhz - (it's stable enough for
    the counter to read... a fast scope shows it approximately as a
    sinewave.

    It seems to be oscillating at about 1/tpd... can't even really pull it
    much with finger capacitance - only about 10 mhz.

    Interestingly, if I short a the floating input-output pair of an unused
    inverter with the scope probe, that runs a bit slower around 260 mhz...
    wheras the gate in use has about 20k of resistance in the feedback
    path.
    I may give your transistor circuit a try, either with components or
    simulation, thanks.
     

  12. What about using a stand-alone LVDS receiver? Eg. Pericom
    PI90LV179W.
     
  13. Tim Shoppa

    Tim Shoppa Guest

    I'm surprised any CMOS 7406 variant really goes to 200MHz! I think you
    got lucky with the one that did work.
    I like high-speed comparators (often called "differential receivers" or
    "LVDS receivers" on the spec sheet) for this.
    The nice thing about differential receivers are:

    1. Easy to set the comparison level.
    2. Lowish input impedance but not too low, such that you set the
    impedance by putting a 50 or 100 or whatever ohm resistor there.
    3. At least for the non-LVDS parts, there's only one or two receivers
    per package so even when it's not SMD it's easy to do dead-bug
    prototyping.
    4. They already have some semblance of defined open-circuit response
    (usually called "fail-safe" for some bizarre reason in the spec sheets)
    to prevent oscillating.
    Usually the hex inverter packages cost a little bit more than the
    4xNAND gate packages. It's nice to have the extra input to act as an
    enable etc. And once you start running these parts into the linear
    region you probably do not really trust using the other sections for
    other functions.
    You can even feed in non-balanced RF subject to some limitations.
    VHF? MMIC's, at least as long as you have only need for AC coupling.

    Tim.
     
  14. Guest

    skrev:
    snip

    The FPGA already has a balanced input, lvds. have you tried that with a
    few resistors
    or maybe a RC filter on signal to set the treshold on one input and the
    signal on the other input? or maybe even a cap into a cmos input
    biased to close but not quite vcc/2

    1Vpp should be plenty, think the thresholds for ldvs is max 100mv

    -Lasse
     
  15. Guest

    That sounds like a good idea, because theoretically we actually have
    some on hand somewhere, I'll have to see if I can scare them up.

    While connecting to the FPGA directly would be simpler, I do like the
    idea of using an external chip as a bit of a 'fuse'. (Though
    transformer coupling into the FPGA should reduce some risk)
     
  16. John  Larkin

    John Larkin Guest

    Second that. We've tested the Xilinx Spartan3 LVDS inputs and they are
    excellent, super-fast comparators.

    John
     
  17. Guest

    Found one and wired it up as the datasheet suggests - cap coupled input
    to half the differential pair, the other side floating at the reference
    output pin voltage with decoupling cap to ground, terminating resistor
    across the pair. Worked quite well.

    The xilinx S3 kit from digilent doesn't seem to be designed with using
    the differential input capability as the pairs are split up all over
    the place. Not certain that I couldn't bias one input of a pair as a
    reference wherever it is and drive the other pin wherever that is, but
    putting it all in a little package seemed simpler.
     
  18. Hal Murray

    Hal Murray Guest

    Be sure to check the output with a scope.

    Years ago, I used a PECL=>TTL part. That was real/old, 5V TTL.
    The problem was that I really wanted a CMOS output and what I
    got was a TTL signal that only went up to 4V or so. We had to
    run it through an AC dead-bug to get what we wanted.
     
  19. Guest

    Good point to keep in mind. In this case though it's all 3.3v
    families, and LVTTL seems to have nearly the same Vih/Vil spec as
    LVCMOS. The part is spec'd with minimum Voh of 2.4v.
     
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