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Input Stage for logic analyzer

Discussion in 'Electronic Design' started by Olaf Petzold, Sep 17, 2005.

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  1. Olaf Petzold

    Olaf Petzold Guest


    I consider to build a logic analyzer. Well, to be flexible with
    different logic families the probe's treshold level should be
    variable, e.g. some mV for 1.8V logic up to 5V for TTL, maybe 18V for
    CMOS (is anyone using this today?).

    My first approach was using comparators like MAX964 driven by 3.3V
    (same as CPLD/FPGA using) and a DAC (@3.3V) with u_ref_max = 1V.
    Unfortunaly, this requires a voltage divider (freq. compensated).

    Are there other ways to perform variable treshold level trigger even
    in a simpler manner? How did solve the commercial analyzer this
    problem found around the net, e.g., or

    Thanks and Regards,
  2. Fred Bloggs

    Fred Bloggs Guest

    I don't know how they did it, but a wideband high dynamic range high
    input impedance buffer driving the attenuator into the comparator will
    do it.
  3. Fred Bartoli

    Fred Bartoli Guest

    I have an old schlumberger 7600 schematics in front of me.

    The probe side is a dual JFET LTP driving the flat cable differential in
    current mode.
    On the analyzer side you have Z matching then a bipolar LPT amplifier and
    then ECL comparators.

    Signal entry is made through a 1/2 divider and a small frequency
    compensation on one JFET gate, while trigger level is sent to the other

    I can scan those bits if you want.
  4. Olaf Petzold

    Olaf Petzold Guest

    Thank you, would be nice (email is a fake, attachements allowed here?)

    Do you see any way to implement something like this using ICs only? I
    don't want to solder a lot of JFETs etc. A 1/2 divider with some Caps
    may be ok. I don't want to transmit the captured signals over a line,
    so there is no need for ecl logic.

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