Injection locking a uC crystal oscillator ?

[Fred Bartoli]

Hello,

I've a CPLD that is across 2 asynchronous clock domains and it becomes,
ahem, somewhat full. Unfortunately I can't upgrade for the next CPLD size
because of package size :-(

So I've thought to eliminate the synchronization FFs.
To do so, I have to make the 2 clock domains synchronous.

The first domain is the system reference clock and is a precise 1.6MHz. It
has to stay as is.
The second domain is an onboard uc (AT90S2313 then ATtiny2313) clock at 8MHz
or maybe 12/16MHz when switching to the ATtiny. (the uc reads an external
serial command bus and translate high level commands to low levels commands
for the CPLD)

I have, for a bunch of reasons, to sync the clocks on board and I've no
place to do it. So I've thought of injection locking the uc clock oscillator
with something like that :

.---------------------.
| AT90S2313/ATtiny2313|
| |
| |
| |
'---------------------'
| |
| _ |
| | | | 8/12 or 16 MHz
+---|| ||---+ crystal
1.6MHz | |_| |
ref clk --- ---
| --- ---
| | |
+----- Z --------+ |
| |
| |
--- |
--- |
| |
| |
=== ===
GND GND
created by Andy´s ASCII-Circuit v1.22.310103 Beta www.tech-chat.de

Did someone tried this ? Is it workable ?
Which side injection point is best ? Amplitude ?
Do I have to expect some startup or other weird problem ?


Thanks,
Fred.

 

[John Larkin]

Hello,

I've a CPLD that is across 2 asynchronous clock domains and it becomes,
ahem, somewhat full. Unfortunately I can't upgrade for the next CPLD size
because of package size :-(

So I've thought to eliminate the synchronization FFs.
To do so, I have to make the 2 clock domains synchronous.

The first domain is the system reference clock and is a precise 1.6MHz. It
has to stay as is.
The second domain is an onboard uc (AT90S2313 then ATtiny2313) clock at 8MHz
or maybe 12/16MHz when switching to the ATtiny. (the uc reads an external
serial command bus and translate high level commands to low levels commands
for the CPLD)

I have, for a bunch of reasons, to sync the clocks on board and I've no
place to do it. So I've thought of injection locking the uc clock oscillator
with something like that :

.---------------------.
| AT90S2313/ATtiny2313|
| |
| |
| |
'---------------------'
| |
| _ |
| | | | 8/12 or 16 MHz
+---|| ||---+ crystal
1.6MHz | |_| |
ref clk --- ---
| --- ---
| | |
+----- Z --------+ |
| |
| |
--- |
--- |
| |
| |
=== ===
GND GND
created by Andy´s ASCII-Circuit v1.22.310103 Beta www.tech-chat.de

Did someone tried this ? Is it workable ?
Which side injection point is best ? Amplitude ?
Do I have to expect some startup or other weird problem ?


Thanks,
Fred.

That config looks OK. I'd inject on the input side of the gain
element. The lower-left C could maybe be an R to maximize injected
harmonics.

Funny, but while walking to work the other day I was thinking about
phaselocking crystal oscillators. I was figuring that, for a 4-pin DIP
crystal oscillator, you could apply an external lock signal to the
unused 4th pin, and it would leak inside the can and lock the
oscillator. Or buy a VCXO and apply DC from a pot to set the
frequency, plus apply the AC phaselock reference to the same pin to
pull it in.

I have to work very hard to keep crystal oscillators, even on
different boards, from locking to each other. Even phantom locking -
brief intervals of phase sticking, even without real frequency locking
- mess up some of the things I'm trying to measure.

The problem with injection locking is that the target oscillator has
to be pretty close to the lock frequency or the pullin won't be
reliable, just like a narrowband PLL.

I think a fair amount of formal work has been done on injection
locking, published in the IEEE journals.

If you do any experiments on this, I'd be interested in the results.

You could make a workable PLL with a tiny logic flipflop, one R, one
C, and one varicap.

How about dumping the crystal and just multiplying the 1.6 MHz to be
the uP clock?

.---------------------.
| AT90S2313/ATtiny2313|
| |
| |
| |
'---------------------'
| |
| R
| |
+-----L-----+
1.6MHz | |
ref clk --- ---
| --- C1 --- big c
| | |
+----- R --------+ |
|
|
L, C1 resonant |
at 8 MHz |
|
|
===
GND

John

 

[Tim Wescott]

That config looks OK. I'd inject on the input side of the gain
element. The lower-left C could maybe be an R to maximize injected
harmonics.

Funny, but while walking to work the other day I was thinking about
phaselocking crystal oscillators. I was figuring that, for a 4-pin DIP
crystal oscillator, you could apply an external lock signal to the
unused 4th pin, and it would leak inside the can and lock the
oscillator. Or buy a VCXO and apply DC from a pot to set the
frequency, plus apply the AC phaselock reference to the same pin to
pull it in.

I have to work very hard to keep crystal oscillators, even on
different boards, from locking to each other. Even phantom locking -
brief intervals of phase sticking, even without real frequency locking
- mess up some of the things I'm trying to measure.

The problem with injection locking is that the target oscillator has
to be pretty close to the lock frequency or the pullin won't be
reliable, just like a narrowband PLL.

I think a fair amount of formal work has been done on injection
locking, published in the IEEE journals.

If you do any experiments on this, I'd be interested in the results.

You could make a workable PLL with a tiny logic flipflop, one R, one
C, and one varicap.

How about dumping the crystal and just multiplying the 1.6 MHz to be
the uP clock?





John

Or use a ceramic resonator for either the frequency multipliation or the
injection locking -- they're much wider bandwidth than a crystal. I suspect
that no matter what you do will require experamentation.

Do you have room for a VCO? Could you phase lock with a 74HC4046?

 

[Fred Bartoli]

Thanks John,

That config looks OK. I'd inject on the input side of the gain
element. The lower-left C could maybe be an R to maximize injected
harmonics.

Funny, but while walking to work the other day I was thinking about
phaselocking crystal oscillators. I was figuring that, for a 4-pin DIP
crystal oscillator, you could apply an external lock signal to the
unused 4th pin, and it would leak inside the can and lock the
oscillator.

Funny idea. I guess it'll be difficult to obtain reliable locking : the
parasitics to the osc die and crystal will be vanishingly small, probably
well under 0.1pf, maybe 0.01pf but that may be worth trying.

Or buy a VCXO and apply DC from a pot to set the
frequency, plus apply the AC phaselock reference to the same pin to
pull it in.

The parasitics could be a bit higher, but if I were in charge to design one,
my first thought would be to carefully low pass the frequency pin.

I have to work very hard to keep crystal oscillators, even on
different boards, from locking to each other. Even phantom locking -
brief intervals of phase sticking, even without real frequency locking
- mess up some of the things I'm trying to measure.

Coupling via supply ?

The problem with injection locking is that the target oscillator has
to be pretty close to the lock frequency or the pullin won't be
reliable, just like a narrowband PLL.

Yep. That why I'll choose my uc crystal frequency to be right on a multiple
of the 1.6MHz.
Just after posting I figured that the best case is for an odd multiple :
both positives and negatives going edges of the ref clock are "in phase with
the xtal", which is not the case for an even multiple.
8Mhz will be perfect, 16MHz will have a pb each other edge. I wonder what
this could give. Worth a try.

I think a fair amount of formal work has been done on injection
locking, published in the IEEE journals.

If you do any experiments on this, I'd be interested in the results.

OK, in such case I'll let you know.

You could make a workable PLL with a tiny logic flipflop, one R, one
C, and one varicap.

How about dumping the crystal and just multiplying the 1.6 MHz to be
the uP clock?

Unfortunately board space is very very very short. It has already been
routed and I know I can't afford to switch to the next cpld size (from
TQFP44 to TQFP100) which is only 4mm more wide.
In a very desperate extremity I might go with your PLL idea. After all I
could probably spare a macrocell from the CPLD in order to gain a dozen.

Thanks,
Fred.

 

[James Arthur]

On 2/29/2004 11:56 AM Pacific Standard Time John Larkin

Funny, but while walking to work the other day I was thinking about
phaselocking crystal oscillators. I was figuring that, for a 4-pin DIP
crystal oscillator, you could apply an external lock signal to the
unused 4th pin, and it would leak inside the can and lock the
oscillator.

Wrong pin -- use Vcc.

I have to work very hard to keep crystal oscillators, even on
different boards, from locking to each other.

Indeed, demonstrating the above -- it seems you've already used Vcc for
locking.

James Arthur

 

[James Arthur]

In message-id: <[email protected]> "Fred Bartoli"

Hello,

I've a CPLD that is across 2 asynchronous clock domains and it becomes,
ahem, somewhat full. Unfortunately I can't upgrade for the next CPLD size
because of package size :-(

So I've thought to eliminate the synchronization FFs.
To do so, I have to make the 2 clock domains synchronous.

The first domain is the system reference clock and is a precise 1.6MHz. It
has to stay as is.
The second domain is an onboard uc (AT90S2313 then ATtiny2313) clock at 8MHz
or maybe 12/16MHz when switching to the ATtiny. (the uc reads an external
serial command bus and translate high level commands to low levels commands
for the CPLD)

I have, for a bunch of reasons, to sync the clocks on board and I've no
place to do it. So I've thought of injection locking the uc clock oscillator
with something like that :

.---------------------.
| AT90S2313/ATtiny2313|
| |
| |
| |
'---------------------'
| |
| _ |
| | | | 8/12 or 16 MHz
+---|| ||---+ crystal
1.6MHz | |_| |
ref clk --- ---
| --- ---
| | |
+----- Z --------+ |
| |
| |
--- |
--- |
| |
| |
=== ===
GND GND
created by Andy´s ASCII-Circuit v1.22.310103 Beta www.tech-chat.de

Did someone tried this ? Is it workable ?
Which side injection point is best ? Amplitude ?
Do I have to expect some startup or other weird problem ?


Thanks,
Fred.

I've injected *many* oscillators, but mostly LCs, not this one.

From my experiences I'd suggest injecting on the driven side, where
impedances are low. Injecting on the oscillator's input side loads and pulls
the oscillator, and complicates start-up. Injection on the input side also
makes the two circuits -- injector and oscillator -- entertainingly
interactive.

Chief considerations include ensuring start-up, adequate pull-in range (so
the thing will lock), and making sure the pull-in range is not exceeded by
drift + initial tolerances.

As others suggested, you might consider another resonator -- pull-in range
for a crystal will be miniscule.

James Arthur