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improving phase noise

Discussion in 'Electronic Design' started by Rene Tschaggelar, Oct 24, 2003.

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  1. I found it rather hard to reach 300MHz or so from
    20MHz with low phase noise. A singlechip PLL appears
    not to be able to do better than 120dBc/Hz through
    to 100kHz

    I haven't checked on a discrete solution yet.
    That means, I'll have to find an odd divider first.

    Is there a way to improve the phase noise performance
    of a PLL ? Perhaps with a resonator ?

  2. Fred Bloggs

    Fred Bloggs Guest

    No- the next step is up, and this will be only 20-30dB improvement, is
    to move to what is called "phase-locked frequency source"- see MITEQ for
    some examples. The 20MHz is not a common reference and will be divided
    by 2-4 to work with most standard product lines.
  3. Mike

    Mike Guest

    Quite possibly - it depends on what your starting point is.

    Resonator-based VCO's typically have better noise performance than
    non-resonator VCO's. Increasing your damping factor may help - if your
    damping factor is too low, peaking in the frequency response will increase
    the phase noise. Depending on the dominant noise source, increasing or
    decreasing the PLL bandwidth may reduce noise further. If you're using an
    active loop filter, you will probably get lower noise by converting to a
    passive filter.

    A tool like Mathcad can be invaluable for problems like this. The PLL loop
    can be modeled relatively easily, and the effects of changes to the loop
    can be viewed almost instantly.

    -- Mike --
  4. I had a look at SimPLL from AnalogDevices. It just supports their
    PLLs though. With one of theirs I wasn't able to get better than
    -120 dBc/Hz.
    On my own, I'd have a tough time in simulating my own PLL.
    How does a divider come in ?
    I tend to doubt rms jitter numbers of 3ps, they are likely not
    able to measure it then.

  5. Mike

    Mike Guest

    Measuring 3ps RMS isn't difficult - the OC-48 parts I've designed (at
    2.488GHz) come in at around 1.5ps RMS. We measure them with a Tek
    Communications Signal Analyzer. Even so, my noise is over 120dBc/Hz until
    around 15MHz (it goes below 110dBc at roughly 10kHz).

    The divider introduces a gain factor in the loop, and effectively
    multiplies the noise from your reference (imagine that the loop keeps the
    noise at the summing node constant - if that's the case, then the noise at
    the VCO side of the divider must be scaled by the divider ratio).

    To model the divider, consider the effect it has on the noise in the time
    domain. Assume the noise is white, and in the time domain it causes t
    seconds of jitter (RMS). The equivalent phase jitter is 2*pi*t/T, where T
    is the signal period. At the divider output, the time domain jitter is
    unchanged - it is still t seconds RMS, assuming the divider doesn't
    contribute significant amounts of noise. However, since the period of the
    divider output is M*T, where M is the divider ratio, the equivalent phase
    noise at the divider output is t/M. In the ideal PLL loop equations, a
    divide by M becomes a 1/M scale factor.

    -- Mike --
  6. Mike

    Mike Guest

    Not quite. What I meant to say was that it's either p/M, where p is the
    phase noise, or 2*pi*t/(M*T). The effect of the divider is to reduce the
    phase noise by a factor of M.

    -- Mike --
  7. maxfoo

    maxfoo Guest

    Try a better phase detector with phase noise of -153dbc/hz.

  8. Regarding the 20MHz, it is rather hard to get anything at all.
    At any frequency almost.
    While the manufacturers *can* do almost everything, there
    is hardly anything on the shelves. And when you only need a few,
    most are not interested. Well, I found a part that looked good.

    I consider this 20MHz, 8ppb from 0 to 70degC, with -120dBc/Hz @10Hz
    and -145dBc/Hz @10kHz for approx 350$ a seldom chance for a reasonable

    Now I should go from this one to 300MHz fixed. Divide by 15 is a bit
    odd, yes. And that should cost me 12dB then.
    The PLL should flatten the lower frequency part down though.

  9. You mean by dividing the phase noise is reduced. This means,
    since the control loop of the PLL works at the lower frequency,
    that the noise there is M times smaller than at the M times higher
    That's what the PLL tools tell me too: 10 times the frequency
    makes 10db more noise. Thats what made me wonder too : a Miteq
    low-noise 15GHz source has phase noise at -70dBc.

    A wideband VCO in a PLL appears not to be it.
    I may have to consider a two oscillator approach :
    Use a VCXO at 300MHz and lock it to the OCXO at 20MHz.

  10. maxfoo

    maxfoo Guest

    The phase noise will be reduced by 10*log(N) if the divider is on the
    Ref of the detector and increase if its on the N inside the loop.
  11. maxfoo

    maxfoo Guest

    oops... should be 20*log(N) in dB, where N is the Division Ratio of
    the divider.
  12. ddwyer

    ddwyer Guest

    I bought a bunch of the best crystal SC OCXOs listed as $500+ at
    16.364MHZ note the SC cut can be driven harder so the design gives -
    170dbc floor.
    CAN BE USED TO DERIVE 1Khz reference; for sale at a very modest price.

    Reply to and avoid my spam congestion.
  13. Fred Bloggs

    Fred Bloggs Guest

    Take a look at the "jitter cleaner" programmable PLL's/buffers such as
    the CDC7005 from Texas Instruments in SiGe with fundamental time jitter
    of 0.5fs- .
  14. Thanks for the hint. I had a look at it.
    Another paper, the SCAA067 at :

    shows the noise. The input clocks can be considered lousy though.
    The shown graphs with -60dBc @10Hz and -100dBc @100Hz both @245MHz are
    way above what I expect. But perhaps with a better reference ...
    I might have a closer look at it.

  15. Ian Buckner

    Ian Buckner Guest

    Hi Rene:

    Does it need to be exactly 300MHz? Could you use, say, one of the
    frequencies divided to 311MHz?

    You may find a SAW filter at a convenient frequency that you could use
    in a VCO, for example 150MHz and a doubler.

  16. Thanks Ian,

    I should have 300MHz or somewhat below. They are used for the AD9854
    DDS synth, to achieve very low phase noise over a wide frequency range.
    Upon studing the appnote to the mentioned CDC7005 chip, I found
    that a PLL (also the CDC7005) takes the stability of the reference
    and the phase noise of the VCO. This means I'd now just need a low noise
    VCO, or rather VCXO, this time at an integer multiple of the 20MHz,
    meaning 260, 280 or 300MHz

  17. Ian Buckner

    Ian Buckner Guest

    There are standard narrow band SAW filters around 280MHz that look
    they could be used for this.

    The phase noise out of a DDS is proportional to the ratio of the
    frequency to the clock frequency.

    For example, if your master clock frequency source had a phase noise
    -120dBc at 10kHz offset at 280MHz (I would expect a SAW based VCO to
    be better than
    this), the phase noise at 10kHz offset on a 28MHz signal from the DDS
    would be
    -140dBc, unless other limitations took effect. Spur levels, for
    example, will be much
    higher than this.

  18. maxfoo

    maxfoo Guest

    the better way to do it is use a 3ghz dro then divide by 10 to get a
    20dB phase noise improvement.
    the dro has a pn of -140dbc/hz @10khz with the divide by 10
    thats -160dbc/hz.....
    the dds pn is 135-140dbc/hz...iirc
  19. John Miles

    John Miles Guest

    Who sells DROs this clean? Got any links?

    -- jm
  20. I've found SAW with bandwidths as small as 70kHz or so.
    That'd be the SAW between the cheap VCO and the DDS. That would only
    lower the wideband noise, but probably not the sidebands of the VCO.

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