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IGBT forward leakage current

Discussion in 'General Electronics Discussion' started by min, Sep 7, 2010.

  1. min

    min

    3
    0
    Sep 7, 2010
    Hi,
    I need help from you all.
    Currently Im testing IGBT forward leakage current.
    Forcing 20V to the VGE, then measuring at the same time.
    The measuring actually fluctuating a lot. Suppose correct measurement should be < 10uA, but it'll from pA to nA then uA jumping around. The reading is not stable.
    From what I understand is the leakage current should be stable over time.
    Am I measuring the correct forward leakage current?
    Need your expertise knowledge and help here.
    Thanks.
     

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  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,191
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    Jan 21, 2010
    Are you trying to measure gate leakage, or leakage across the device?
     
  3. Militoy

    Militoy

    180
    0
    Aug 24, 2010
    Your diagram looks good for measuring gate-emitter leakage current [IGES -
    Leakage current between gate and emitter with collector-emitter short-circuited (VCE = 0); at maximum gate-emitter voltage VGE]. Your use of the term "forward" is a little confusing - I'm assuming you mean with gate at positive polarity with respect to emitter, as opposed to negative?

    Maybe the trouble is with the layout of your test setup - when measuring very low currents, it's possible for stray noise to mess up your readings. Make sure all your leads are kept as short as possible, twist wire pairs to cancel noise, and make sure connections are secure.
     
  4. min

    min

    3
    0
    Sep 7, 2010
    Yes. the forward means forcing positive voltage to gate respect to emitter.
    Attached the measurement graph. Plot 0 is voltage forced. Plot 1 is current measured.
    From the graph, when my voltage at 20V, the current start to drop.
    Any problem with my setup?
     

    Attached Files:

  5. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,191
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    Jan 21, 2010
    It looks like you're measuring capacitance, not leakage.

    You show a constant current proportional to the instantaneous change in voltage between the gate and the other terminals.

    Whilst I am pretty sure you could use those figures to calculate the capacitance, they are consistent with zero gate leakage (within the limits of your measuring equipment)

    edit: to measure gate leakage you should be looking for a difference in the "zero" current when the gate voltage is zero and when it is 20V. If your equipment is sensitive enough, you may see a slight difference. It may be buried in noise from your measuring equipment, so you may have to average many measurements and see if there is a statistically significant difference.
     
    Last edited: Sep 8, 2010
  6. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    25,191
    2,693
    Jan 21, 2010
    if the scales are ms, V, and A, then I make the gate capacitance about 2.8nF (2800 pF)
     
  7. Militoy

    Militoy

    180
    0
    Aug 24, 2010
    Agreed - your graph looks like a measurement of the test leads and test equipment limitations - I wouldn't exactly call it "unstable" - I would just call it imperfect.

    It reminds me of a test graph you might get from a simulation - if you put a few "real world' parasitics into the sim. You might try for a quick reality check - setting aside the NI test set and repeating the test on a bench with more basic equipment. Sometimes the ATE itself throws a monkeywrench into the works.
     
    Last edited: Sep 8, 2010
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