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ICSP and timing

Discussion in 'Electronic Design' started by Jon Slaughter, Sep 27, 2007.

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  1. In section 4 it discusses the protocol for ICSP on micropics.

    As far as I can tell its quite easy to do but what concerns me is the
    initial command after reset. It seems that all one really has to do is wait
    70 clock cycles and it doesn't matter what the data line does because in
    note 1 it says they are forced to 0. Normal commands take a total of 32
    cycles. Everything seems pretty much straight forward I suppose and I'm
    probably making it harder than it is(just really want to be 100% sure I
    understand it).

    In section 5.1.1 it says

    "After the programming executive has processed the
    command, it brings PGDx low for 15 ?sec to indicate to
    the programmer that the response is available to be
    clocked out. The programmer can begin to clock out
    the response 20 ?sec after PGDx is brought low, and it
    must provide the necessary amount of clock pulses to
    receive the entire response from the programming

    and shows a timing diagram in figure 5.2.

    What I'm really concerned about is that it says I the chip will bring PGDx
    low for 15us then it says after 20us the programmer can start clocking the

    I assume that I could wait anytime as long as its greater than 35us? The
    problem is I would have to poll the data line to check when the line changes
    but this is not a good situation for me.

    If I cannot poll in the 15us or so that its low do I loose it? It says it
    brings it low for 15us and hence meaning that it then brings it back high or
    "releases" it? I don't have interrupts so I could use that to catch when it
    changes and there is a big chance I could not poll it within the 15us time
    frame(if my task is interrupted for other reasons then it could be several
    ms before I get control again).

    This seems to be the main problem I have in that I have to "poll" and it
    seems as if there is an exact time frame I have to do it.

    It seems though I could just "hack" it by just making sure I wait more than

    One last thing that I'm unfamiliar with is in the timing diagrams they show
    a level that is inbetween high and low. In fig 5.2 they do this at P10.

    What in general does the 1/2 level mean?

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